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AMD broadcasts the Spartan UltraScale+ FPGA household for cost-sensitive and IO-intensive purposes

AMD broadcasts the Spartan UltraScale+ FPGA household for cost-sensitive and IO-intensive purposes

2024-03-10 21:01:35

The Spartan UltraScale+ FPGA household is the most recent inclusion to AMD’s Cost-Optimized portfolio, a sequence of FPGAs designed to stability value, energy, and kind issue with affordability. The UltraScale+ FPGA household is designed for cost-sensitive, low-power purposes requiring excessive I/O rely and substantial safety.

amd spartan ultrascale+

Gadgets within the Spartan UltraScale+ household supply a excessive I/O to logic cell ratio for FPGAs in-built 28nm and decrease course of expertise (the very best within the business, in accordance with AMD), devour as much as 30% much less energy than in comparison with the earlier era, and have strong safety features that outclass the remainder of the Value-Optimized portfolio.

This FPGA household is constructed on the identical UltraScale+ structure as previous Artix and Zynq products. They’re the primary AMD UltraScale+ FPGAs to characteristic a hardened DDR reminiscence controller and PCIe Gen4 x8 help, “offering each energy effectivity and future-ready capabilities for purchasers.”

amd spartan ultrascale+ block diagram

AMD Spartan UltraScale+ specs:

  • System Logic Cells – As much as 218K
  • Reminiscence
    • On-Chip Reminiscence: Block RAM for low latency, excessive throughput, and UltraRAM
    • Exterior Reminiscence: LPDDR4x and LPDDR5 as much as 4266 Mb/s (exhausting MC), and DDR4 (comfortable MC) IP as much as 2400 Mb/s
  • I/O
    • I/O Rely: 572
    • Varieties:
      • Excessive Density I/O (HDIO) as much as 3.3V,
      • Excessive-Efficiency I/O (HPIO) as much as 1.8V,
      • XP5IO as much as 1.5V, supporting 3200 Mb/s MIPI and 1800 Mb/s LVDS
    • PCIe: Gen4 x8
    • Transceivers – As much as 8 GTH transceivers supporting as much as 16.3 Gb/s
  • Safety – NIST-approved post-quantum cryptography, distinctive system identification, everlasting tamper penalty for system safety, and side-attack safety by way of DPA countermeasures

The Spartan UltraScale+ FPGA sequence is primarily focused for embedded imaginative and prescient, healthcare, industrial networking, robotics, and video purposes in accordance with the press release. The excessive I/O rely will allow the FPGAs to interface with a variety of sensors and paired with the programmable logic make it attainable to regulate the sensors in actual time and with low latency.

On the software program finish, the Spartan UltraScale+ FPGA household (together with the remainder of AMD’s FPGA and adaptive SoCs lineup) is supported by AMD’s Vivado Design Suite and Vitis Unified Software program Platform. This permits each {hardware} and software program designers to leverage the “productiveness advantages of those instruments by way of a single designer cockpit from design to verification.”

AMD Spartan UltraScale+ samples and analysis kits are anticipated to be obtainable for sampling and analysis within the first half of 2025. Documentation is presently obtainable and instruments help beginning with the AMD Vivado Suite in This fall 2024. To study extra in regards to the Spartan UltraScale+ FPGA household and what it affords, make sure to go to the product page.

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