An open 32-bit RISC/Vector ISA
MRISC32 is a 32-bit RISC/vector ISA
(instruction set architecture).
A number of the targets of the ISA are:
-
Create a clear, fashionable ISA that’s equally engaging to software program, {hardware} and
compiler builders. -
Allow excessive efficiency implementations, with good scalar and vector integer and
floating-point help. -
Allow useful resource and vitality environment friendly implementations of each in-order and
out-of-order machines.
MRISC32 is impressed by architectures resembling Cray-1,
MIPS and
RISC-V, and tries to mix the
good elements with out repeating some unlucky design selections (e.g.
delay slots and lack of
useful addressing modes).
MRISC32-A1
The primary implementation of the MRISC32 ISA is MRISC32-A1,
which is a gentle processor carried out in moveable VHDL, appropriate for working
on an FPGA. It’s a 9-stage pipelined, single situation, so as structure (i.e.
it could execute at most one operation per clock cycle), and it implements the
total MRISC32 ISA.
The CPU simply suits in a low- to mid-range FPGA, such because the
MAX® 10,
by which it consumes about 12K logic components and runs at 70-100 MHz
on the time of writing. It will also be configured to make use of a lot much less assets
(all the way down to 30% of the complete design) by disabling sure options, resembling
floating-point help.
MC1
The MC1 (brief for
MRISC32 Pc 1), is a small open supply pc for
FPGA:s, internet hosting an MRISC32-A1 CPU core. Certainly one of its principal options is
its versatile video subsystem that makes it appropriate for graphical
purposes.
The MRSIC32 ISA and the MRISC32-A1 implementation are nonetheless in improvement.
A number of elements resembling exception dealing with and reminiscence administration are nonetheless
undefined.