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Antmicro · Accelerating digital block design with Google’s open supply Mid-Degree Synthesis XLS toolchain

Antmicro · Accelerating digital block design with Google’s open supply Mid-Degree Synthesis XLS toolchain

2023-11-03 14:53:09


Open supply instruments, Open ASICs, Open FPGA

Digital circuits have gotten an increasing number of sophisticated because of fixed know-how improvement and growing consumer expectations. In response to this rising complexity, improvement instruments that present a better degree of abstraction for digital system designers have been rising in prominence.

Alongside HDL turbines akin to Chisel, SpinalHDL, Migen and Amaranth, which have been gaining some reputation amongst extra software-minded builders, there are even newer approaches promising vital productiveness will increase like Google’s open supply XLS toolchain. Utilizing an encode/decode accelerator that Antmicro has been growing and contributing to XLS for instance, this text will describe how XLS can be utilized to construct, adapt and take a look at digital designs. In fact XLS’ capabilities transcend codec blocks, however given the framework’s origin in serving to Google ship environment friendly transcoding options, they function an excellent illustration of the power of this method.

Accelerating digital block design with Google’s XLS illustration

XLS as a Mid-Degree Synthesis toolchain

XLS (standing for Accelerated {Hardware} Synthesis) is a completely open supply toolchain created by Google that produces synthesizable designs from high-level descriptions of their performance. Recognized limitations of ordinary Excessive-Degree Synthesis (HLS) approaches to non-trivial issues are properly acknowledged, so XLS tries to strike an excellent steadiness between succinctness and adaptability, to the purpose of referring to itself as a “Mid-Degree Synthesis” device. This emphasizes that regardless of the offered degree of abstraction, the consumer could configure low-level particulars of the stream to create designs which are each simple to motive about and environment friendly. XLS offers designers management over many properties within the circuit that conventional HLS options would summary away with out explaining what the device did and why. XLS as a substitute chooses to make choices extra express (with the ability to specify issues like pipe levels explicitly, acceptable worst case throughput, explicitly figuring out what SRAMs are launched / alongside which channels, surfacing detailed and clear scheduling studies, and so on.). The usage of procs (single stateful XLS components) enables you to discover a midpoint between all the time blocks you’d create in RTL vs. loops which you’ll’t make certain what the HLS instruments will translate into, so you may add construction with procs as structured however multi-cycle concurrent components as a sort of “all the time blocks on steroids”.

XLS makes use of DSLX, a Rust-like DSL which the XLS group believes can supply vital productiveness benefits. DSLX is transformed to so-called XLS IR which then will get compiled all the way down to RTL.

The principle goal of the XLS challenge is to allow productive collaboration between software program and {hardware} engineers by creating a typical methodology for designing digital circuits, primarily based on a software-driven method. Because of this, the identical design description can be utilized to generate a software program mannequin of the circuit and a last RTL description in Verilog or SystemVerilog. This type of a typical denominator method permits each teams of engineers to cross their area boundaries, perceive one another’s price fashions, and share information and expertise. XLS is thus meant to assist degree up the {hardware} improvement course of with the rate, composability, modularity and retargetability recognized from the software program world.

XLS use instances

The advantages of XLS are significantly evident within the design of digital circuits with vital algorithmic complexity, because the offered layer of abstraction permits the consumer to focus extra on the designed performance, relatively than low-level implementation particulars. Due to this, XLS is a good match for designing circuits primarily based on video encoding, image processing, encryption algorithms, compression algorithms, or accelerating computation for AI processing.

Nevertheless, XLS isn’t meant solely for complicated designs. The examples offered within the XLS repository show the toolchain’s versatility and present its many attainable purposes.

XLS in motion

In collaboration with Google, Antmicro has been working to show how XLS can be utilized for implementing compression algorithms akin to Run-Length Encoding (RLE) and Dictionary Based Encoding (DBE) as open supply ASIC-targeted blocks. The encoders and decoders have been carried out in DSLX. The extent of abstraction enabled by DSLX allowed for exploring completely different architectural decisions, and incremental refinement within the implementation of the encoders. This ensuing contribution is extra normal and parameterizable than conventional HDLs would permit with out introducing vital complexity.

Implementing RLE

Let’s take a look at the RLE block for instance. The initial version of the encoder, which was quite simple to implement, used a proc to sequentially learn incoming knowledge and compress it into symbol-value pairs.

To allow extra sensible encoder designs, we then proceeded so as to add a extra superior model of the block able to processing a number of symbols concurrently. A subsequent reimplementation consists of 4 processes that talk with one another, as detailed within the picture beneath.

The primary block – much like the preliminary implementation – is liable for taking the enter and decreasing it to pairs of symbols and the variety of its occurrences. The second ingredient of the encoder shifts the beforehand emitted pairs and adjusts them for additional processing. Each of those components have an empty state. The following block takes the ready knowledge and combines it with the details about beforehand processed symbols. The final ingredient is liable for adjusting the width of the output knowledge to the receiver interface.

Total, we are able to break down the info processing into 4 levels: discount, alignment, compression, and output era. The division of accountability allowed the specialised blocks to effectively course of knowledge and gave us an opportunity to completely take a look at every performance individually.

Multisymbol Run Length Encoder diagram

See Also

Testing and verifying the design

Along with the encoders, we created multiple tests to confirm that the designs work accurately. Moreover, the internal verification mechanism built into XLS ensured that the generated RTL sources correspond with the software-model that we examined completely earlier than. Later, to research the throughput of the core, we added assist for the favored Python-based Cocotb framework into the XLS toolset, which allowed us to create reusable Python exams analyzing real-life efficiency of the designs transformed to RTL code.

Nearer to silicon with SKY130 and ASAP7

Since XLS is supposed to allow production-grade block design for ASICs, one other ingredient of the challenge was to combine open supply bodily design tooling into the XLS toolchain. This allowed for producing silicon layouts utilizing the SkyWater 130nm and ASAP7 PDKs and shutting the design loop, from software program written in DSLX all the way down to GDS. Having a completely open supply stream is nice for retaining the framework well-tested with available efficiency parameters that may be tracked over time.

The bodily design stream makes use of Yosys for synthesis and OpenROAD for floorplanning, placement, clock tree synthesis and design routing. Each step within the course of leverages normal cell definitions and design guidelines from the chosen PDK. The whole workflow is constructed as a group of reusable guidelines for the Bazel construct system which is utilized in your complete XLS challenge.

Beneath you may see the Run Size Encoder silicon design in Klayout and its visualization created with gds_viewer:
Run Length Encoder silicon design in Klayout

Visualization of Run Length Encoder in [gds_viewer](

Renode XLS integration

Since fabrication of high-end chips is pricey and time-consuming, and in the end the ultimate efficiency and value of silicon depends on the software program that runs on high of it, the power to check the system in a sensible HW/SW context from the very starting is invaluable. Due to this fact, in parallel to the design itself, we determined to create a completely useful demonstrator showcasing the utilization of the created encoders for real-life purposes on a RISC-V platform. Co-simulation of digital designs using Verilator has been out there in Antmicro’s Renode simulator for a while, and was an inspiration for creating an identical integration for XLS. One of many options that satisfied us to take this effort is the JIT compilation out there in XLS that permits executing design fashions at native machine pace. The Renode-XLS integration is in progress and might be described in a future weblog word.

Accelerating digital design with Antmicro and XLS

XLS is a framework centered on developer productiveness and because of its flexibility and in depth verification capabilities it permits for speedy improvement of digital designs. The brand new RLE and DBE constructing blocks, along with contributions to the framework itself from Antmicro enhance the XLS ecosystem for sensible utilization past its unique authors. In case you are taken with growing and testing digital designs concentrating on FPGAs or ASICs utilizing SW-driven methodologies, contact Antmicro at

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