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Characterizing Gaming Workloads on Zen 4 – Chips and Cheese

Characterizing Gaming Workloads on Zen 4 – Chips and Cheese

2023-09-06 17:19:34

AMD didn’t current plenty of new data concerning the Zen 4 core at their Sizzling Chips 2023 presentation. Uops.info has measured execution throughput and latency for directions on Zen 4. We’ve dug deep into Zen 4’s microarchitecture in a set of articles as well. Nonetheless, the Zen 4 core structure continues to be an necessary element each of AMD’s Sizzling Chips shows. I’m due to this fact going to throw a little bit of a curveball, and take a look at Zen 4’s efficiency in gaming workloads, and use efficiency counters to get visibility into how Zen 4 internally handles gaming. That ought to assist present context to each of AMD’s shows that contain Zen 4.

Right here, I’m testing a few video games on my Ryzen 9 7950X3D, particularly The Elder Scrolls On-line (ESO) and Name of Responsibility: Black Ops Chilly Struggle (CoD Chilly Struggle). On ESO, I’m grinding out expertise within the Blackrose Jail area. In CoD Chilly Struggle, I’m taking part in the Outbreak Collapse mode within the sport’s zombies mode. I’m utilizing my 7950X3D, which options 16 Zen 4 cores organized in two complexes. Considered one of these has 96 MB of L3 cache, because of AMD’s 3D V-Cache characteristic. For some stage of consistency, each video games have affinity set to the VCache enabled CCD. Core efficiency increase was disabled, giving a most clock of 4.2 GHz throughout all cores.

Slide from AMD’s presentation at Sizzling Chips 2023

Zen 4 is AMD’s newest core structure, and represents an iterative enchancment over Zen 3. Alongside that, it brings all of the goodies you’d count on from a node shrink. In a very cool transfer, Zen 4 brings a brand new set of efficiency monitoring occasions that lets us characterize utilization on the pipeline slot stage. Intel has been in a position to do that to some extent since Sandy Bridge, however efficiency monitoring {hardware} in AMD’s CPUs may usually solely do cycle stage accounting. Zen 4 modifications this.

Ha, I’ve a 7950X3D

My purpose is to get a common image of how gaming workloads behave on AMD’s Zen 4. As a result of these are multiplayer video games, I count on plenty of variation and outcomes that received’t be completely repeatable. Additionally, knowledge was collected over a number of passes as a result of Zen 4 solely has six programmable efficiency counters, and I needed to test greater than six occasions to get an honest image. Subsequently, my purpose is to get a excessive stage image of challenges confronted by Zen 4 in these workloads, quite than drilling down figures to the final proportion level.

I like to recommend going over our prior articles on Zen 4’s core and memory subsystem.

Excessive Stage

Each video games expertise low common IPC. Zen 4 is able to sustaining 6 micro-ops per cycle. Most directions decode right into a single micro-op, so Zen 4 is roughly 6 directions large as properly.

Zen 4’s sustained throughput is proscribed by the 6-wide rename stage, any throughput misplaced there can’t be recovered by racing to catch up in a while. Like Intel’s CPUs, Zen 4 can account for misplaced rename throughput on the per-slot granularity.

Each gaming workloads are overwhelmingly frontend sure. They’re considerably backend sure as properly, and lose additional throughput from unhealthy hypothesis. Helpful work occupies a comparatively minor proportion of obtainable pipeline slots, explaining the low IPC.

Frontend

As a result of a plurality of obtainable pipeline slots are frontend sure, let’s begin there. By AMD’s definition, a slot is frontend sure if the renamer had accessible slots that weren’t utilized as a result of no micro-ops have been accessible from the frontend. AMD’s Processor Programming Reference (PPR) additional splits frontend sure slots into latency and bandwidth sure classes. Particularly, slots are thought of latency sure if the frontend doesn’t provide any micro-ops throughout that cycle. If the frontend provided some micro-ops however not sufficient to fill all six slots, the unfilled slots are thought of bandwidth sure.

Zen 4’s frontend is overwhelmingly latency sure. Frontend latency can come from cache misses, in addition to department predictor associated delays. We will begin to unravel the frontend latency downside by the place directions are coming from. Zen 4 can feed its pipeline from three completely different sources. A 144-entry loop buffer supplies very quick micro-op supply for tiny loops. Then, a 6.75k entry micro-op cache tries to comprise scorching sections of code. Lastly, a 32 KB L1 instruction cache focuses on offering excessive caching density by straight caching x86 directions, and takes benefit of x86’s shorter, variable size directions.

Neither sport has plenty of small, scorching loops, so the loop buffer is nearly a non-factor. The micro-op cache enjoys 70-81% hitrate in each video games, indicating that they spend plenty of time executing code with good locality. The instruction cache does an honest job with 71-77% hitrate, however misses per instruction reveals a special image. 17-20 MPKI L1i is sort of a excessive miss fee. The L2 cache helps backstop these L1i misses, however sometimes some instruction fetches fall by way of L2 as properly. Sadly, Zen 4’s efficiency monitoring occasions can’t distinguish between code fetches from L3 or DRAM.

Instruction cache misses aren’t essentially an enormous downside. We’ve seen in microbenchmarks that Zen 4 is able to sustaining near 4 IPC even when working code from L2 or L3. Nonetheless, that assumes the department predictor generates targets far sufficient forward to cover latency. The L2 prefetcher possible helps too, notably for very predictable patterns like linear code fetches. However ESO and COD Chilly Struggle have a ton of branches. On common, there’s a department each 4 to 5 directions.

Subsequently, the department predictor is closely concerned in protecting the frontend working easily. To comply with branches rapidly and maintain efficient department latency down, Zen 4 has a multi-level BTBs (department goal buffers) that keep in mind the place not too long ago executed branches went.

The 1536 entry L1 BTB can ship taken department targets again to again, so misplaced throughput there can be counted as frontend bandwidth sure (simply from shedding directions fetched previous a taken department). The bigger 7680 entry L2 BTB causes three “bubble” cycles within the department predictor, which means three cycles of fetch tackle era get misplaced. Predicting oblique branches incurs an analogous penalty. In a workload with fewer branches, these bubbles is likely to be tolerable as a result of the frontend can present fairly excessive bandwidth in a straight line.

From the Veyron V1 article. Zen 4 does aligned 32B fetches from the L1i and successfully aligned 64B fetches from the op cache

For instance, the micro-op cache can ship 9 micro-ops per cycle, letting it run forward of the renamer and refill an op queue in entrance of it. Any op cache fetch hiccups would run down some op queue entries earlier than the frontend catches again up. Equally, the L1 instruction cache can present 32 bytes per cycle, which corresponds to eight or extra x86 directions in integer code. Nonetheless, taken branches will spoil that frontend bandwidth as a result of department targets could also be properly after the beginning of a fetch-width aligned block, and any micro-ops or instruction bytes fetched after a taken department aren’t helpful. Subsequently, BTB efficiency issues when the frontend is struggling to maintain up.

Zen 4’s L1 BTB catches the overwhelming majority of branches, however we nonetheless see a number of slip over into the L2 BTB. Oblique department predictions additionally see a 3 cycle penalty, and together with meaning we see a 3 cycle taken department penalty in about 1 in 100 directions. BTB latency isn’t an enormous deal right here, and AMD has carried out an excellent job making the primary stage BTB giant sufficient.

ESO apparently has plenty of oblique branches. Observe that an oblique department will be dealt with by the common BTBs if it repeatedly goes to the identical goal

If the department goal isn’t cached in any respect, we have now an even bigger downside. Zen 4 handles that case by calculating the goal when the department instruction arrives on the decoders. Whereas such “decoder overrides” don’t occur fairly often, they are often very costly as a result of they stop the department predictor from working forward of the frontend. In spite of everything, the decoder can’t calculate the department goal till the department bytes present up on the core. If a decoder override factors to a department goal in L2, you’re round a dozen cycles of misplaced frontend throughput. If the department goal is in L3, count on the frontend to spend the subsequent 40+ cycles with out directions coming in, because of cache latency. Subsequently, decoder overrides probably end in extra misplaced frontend throughput than L2 BTB or oblique predictor latency, notably if most branches that undergo decoder overrides are fetched from L3.

Instruction TLBs

Cache latency will be exacerbated by tackle translation penalties. Zen 4 caches instruction-side tackle translations with two ranges of translation lookaside buffers (TLBs).

For hitrate calculation, I’m treating L1i fetches as iTLB accesses

The 64 entry iTLB sees excessive hitrate if we rely each L1i entry as a iTLB entry, however misses per instruction tells one other story. COD Chilly Struggle sees an excellent variety of iTLB misses, suggesting its instruction footprint goes past 256 KB. ESO does a bit higher, however each MPKI and hitrate metrics will be misleading. The frontend will solely provoke one L2 iTLB or web page stroll in response for a number of iTLB misses to the identical web page, so a single iTLB miss might be holding again a number of instruction fetches.

Happily Zen 4’s 512 entry L2 iTLB is sufficient to deal with most instruction fetches. Misses are moderately uncommon on each video games, indicating that instruction footprint doesn’t usually transcend 2 MB.

Dangerous Hypothesis

We beforehand lined how rapidly the department predictor can feed the frontend. Velocity is necessary, however accuracy is simply too. Mispredicting a department is sort of a horrible model of a decoder override. You incur frontend cache latency, and must discard any directions pulled into the backend after the mispredicted department. We frequently see folks discuss pipeline size from fetch to execute, however that’s actually only a minimal determine. Department mispredicts can incur a lot increased prices if the mispredicted department sat within the scheduler for dozens of cycles as a consequence of dependencies. The core may have fetched piles of directions from the unsuitable path within the meantime, and all of that work might be wasted.

However, checkpointing permits the CPU to get better rapidly from a mispredicted department and overlap the mispredict penalty with execution of micro-ops from earlier than the mispredicted department. To raised characterize the price of mispredicted branches, we will deal with how a lot renamer throughput was spent pulling in micro-ops that have been by no means retired. A micro-op that’s not retired by no means will get its outcomes made remaining and program seen. Technically the CPU can throw work out for different causes, however department mispredicts are the principle trigger.

Utilizing the methodology instructed in Zen 4’s PPR

AMD has invested closely in making a really succesful department predictor. It does obtain very excessive accuracy, however we nonetheless see 4-5 mispredicts per 1000 directions. That ends in 13-15% of core throughput getting misplaced as a consequence of happening the unsuitable path.

Once more, we have now an issue as a result of these video games merely have a ton of branches. Even with over 97% accuracy, you’re going to run into mispredicts pretty usually if there’s a department each 4 to 5 directions. With reference to frontend throughput, a mispredict is mainly a worse model of a decoder override. Department mispredict penalty will range relying on the place the right goal comes from, and getting a goal from L2 or L3 may simply add dozens of cycles on prime of the minimal department mispredict penalty. I count on AMD and everybody else to maintain investing closely within the department predictor as they struggle for increased efficiency.

Backend Certain

When the renamer isn’t under-fed by the frontend or being fed the unsuitable stuff, it usually can’t ship a micro-op downstream as a result of it couldn’t allocate a required useful resource within the backend. The rename stage continues to be in-order, so if any instruction wants an entry in a construction that’s full, no different micro-ops after it may well proceed.

From the Zen 4 Processor Programming Reference

Zen 4’s PPR suggests breaking down backend sure stalls by going all the best way ahead to the retire stage, the place instruction outcomes are dedicated in-order. There, a brand new efficiency monitoring occasion lets us break down why retirement was stalled.

ROB empty simply reveals when the core is so frontend sure that the backend finally ends up with no work to do

Reminiscence masses are the largest offender. Including extra execution models or bettering instruction execution latency wouldn’t do a lot, as a result of the issue is feeding these execution models within the first place. Out of order execution can disguise reminiscence latency to some extent by shifting forward of a stalled instruction. How far forward it may well go depends upon what assets the backend has to trace in-flight operations. Zen 4’s schedulers, register information, and numerous queues are solely so huge. Finally, one thing will fill and forestall the backend from receiving extra directions.

Slide from AMD’s Sizzling Chips 2023 presentation, depicting Zen 4’s out of order execution engine

Zen 4 supplies efficiency monitoring occasions to interrupt down what construction crammed up and restricted reordering capability, so let’s have a look.

Each video games fill the reorder buffer very often in comparison with different backend assets, so AMD’s designers hit a fairly good steadiness when sizing backend register information and queues. Zen 4’s integer and FP register information not often fill. The shop queue does stand out in COD Chilly Struggle. It’s additionally the highest cause for a backend sure renamer stall in ESO if we exclude the ROB. Nonetheless, making a bigger retailer queue might be troublesome as a result of each load probably has to test the tackle of each prior retailer for forwarding alternatives.

Numbering the schedulers to make issues clear

Zen 4 makes use of a distributed scheduling scheme that’s much less easy to optimize than the unified schedulers we see with Intel, as a result of we may get a dispatch stall if any particular person queue fills. All the scheduling queues put collectively are solely chargeable for 7.08% and 4.82% of stalled renamer cycles in ESO and COD Chilly Struggle, respectively. One specific integer scheduling queue stands out, since it may well deal with branches, reminiscence accesses, and common ALU directions.

AMD may tackle this by including extra entries to that scheduling queue. However as everyone knows, dealing with latency is only one strategy to go about issues. Higher caching means you don’t must cope as laborious, so let’s take a look at the data-side reminiscence hierarchy.

Cache and Reminiscence Entry

Step one in performing a reminiscence entry is to translate the digital tackle utilized by applications into bodily addresses. Zen 4 makes use of a two stage TLB setup to hurry this up. The 72 entry first stage DTLB suffers fairly a number of misses, and has an particularly laborious time in ESO. DTLB misses are sometimes caught by the 3072 entry L2 DTLB, however that provides an additional 7-8 cycles of latency.

Counting LS dispatches as DTLB lookups for hitrate calculation

Simply as with the frontend, DTLB misses will be deceptively low as a result of the core will solely queue up one TLB fill request if a number of close by directions undergo a TLB miss. With that in thoughts, 6-8 DTLB MPKI is definitely fairly excessive. The identical applies for L2 DTLB misses. L2 DTLB misses are costlier as properly as a result of web page walks can contain a number of dependent reminiscence accesses.

After tackle translation, reminiscence accesses will be serviced by a triple stage cache setup. The 32 KB L1D is quite small and sees plenty of misses. Most of those are caught by L2, which does a reputable job as a mid-level cache. Then, the 7950X3D’s giant 96 MB L3 helps catch almost all L2 misses. VCache is due to this fact doing an excellent job of decreasing backend stalls.

For L1D hitrate, LS dispatches are counted as L1 accesses. L1 misses counted with PMC0x044, Any Information Cache Fills by Information Supply

Once more, efficiency counters are monitoring cache refills. A number of directions accessing the identical 64B cacheline will solely provoke one refill request, so count on extra directions to be affected by cache misses than the rely right here would straight recommend.

See Also

L3 Cache, Cache Controller Perspective

After we regarded on the frontend, core counters couldn’t distinguish between L1i fills from L3 or DRAM. Nonetheless, I believe an excellent chunk of code fetches went out to DRAM. L3 hitrate is far decrease after we test efficiency counters on the L3 cache, which see all requests from the cores.

In a roundabout way corresponding to the hitrate outcomes from our previous article on Zen 4’s VCache, as a result of COD Chilly Struggle has acquired a number of patches since then

If the frontend does must run code from L3, throughput might be properly under 4 bytes per cycle. That will clarify among the frontend latency sure cycles.

Latency or Bandwidth Certain?

Zen 4’s backend is primarily reminiscence sure in each video games. That brings up the query of whether or not it’s latency or bandwidth sure. In spite of everything, bandwidth and latency are linked, since you’ll see a pointy latency enhance as you attain bandwidth limits and requests begin backing up in queues.

We will benefit from that by monitoring what number of L1D misses the cores have queued up. Zen 4 tracks L1D misses in what AMD calls miss tackle buffers (MABs). They’re roughly equal to Intel’s fill buffers, and are generically known as miss standing dealing with registers (MSHRs). Zen 4 supplies a efficiency monitoring occasion that may monitor what number of MABs are allotted every cycle. As a result of reaching excessive bandwidth means protecting sufficient requests in flight to cover latency, we will infer that the cores are asking for lots of bandwidth if MAB occupancy is excessive. In distinction, if only some MABs are allotted, then we’re possible latency sure.

Depend masks area used to trace cycle counts when MAB occupancy exceeded a sure stage

MAB occupancy is often low. Zen 4 is usually ready for knowledge from L2, L3, or reminiscence, however not often had greater than 4 such excellent requests. For context, Intel’s Core 2 had eight fill buffers, and Golden Cove has 16. Zen 4 not often wants that stage of reminiscence stage parallelism, indicating that bandwidth isn’t a problem.

We will additionally deal with reminiscence bandwidth by common request latency. Zen 4 introduces a brand new efficiency monitoring occasion that randomly samples latency for requests despatched to Infinity Cloth. This can be a neat enchancment over prior Zen generations, the place you would calculate L3 miss latency in cycles by observing miss rely and pending misses per cycle, however getting latency in nanoseconds was troublesome except you locked clock frequencies.

Common DRAM latency is properly under 100 ns, so requests aren’t piling up on the reminiscence controller. Bear in mind this determine measures DRAM latency from the L3 perspective, not the core’s perspective. Reminiscence latency seen by software program goes to be barely increased, as a result of the core has to test L1D, L2, and L3 earlier than going to DRAM.

Last Phrases

COD Chilly Struggle and the Elder Scrolls On-line each have very giant instruction footprints with tons of branches, inflicting main issues for the in-order frontend. Each video games additionally characteristic giant data-side footprints, however the out-of-order backend is healthier positioned to deal with data-side reminiscence entry latency.

Zen 4’s enhancements over Zen 3 are concentrated in the correct areas. The bigger ROB and supporting buildings assist soak up reminiscence latency. Monitoring extra branches at sooner BTB ranges helps the frontend take care of large instruction footprints, as does the bigger L2 cache. However AMD nonetheless has room to enhance. A 12K entry BTB just like the one in Golden Cove may enhance frontend instruction supply. Department predictor accuracy can all the time get higher. The shop queue’s measurement has not saved tempo and typically limits efficient reordering capability. That mentioned, the shop queue is an costly construction. AMD didn’t need to make retailer queue entries 512-bits large for AVX-512, and including extra retailer queue entries would additionally imply space development.

Making the STQ entries 512b would have meant doubling the STQ knowledge storage. That space development would haven’t been in step with our strategy to AVX-512 on Zen4.

Kai Troester, AMD

From the information facet, bigger out-of-order queues and caching would clearly assist. AMD has spent plenty of effort right here. Zen 4’s 1 MB L2 cache and stacked 96 MB L3 cache each assist enhance common latency for directions that entry reminiscence.

AMD needs to be recommended for not losing space and energy chasing bragging rights. Zen 3’s scheduler structure was already fairly good, and protecting it in Zen 4 is sensible. Matching Golden Cove’s 6-wide decoder would have been nice for bragging rights, however received’t have an effect on efficiency a lot. Widening the general pipeline would even be a waste, as a result of feeding that core width is extra necessary than having extra width.

Lastly, this piece solely seems at two multiplayer video games. Zen 4 isn’t only a gaming CPU, and has to carry out properly in quite a lot of purposes. If time permits, I plan to have a look at a few of these in-depth and see how they differ from video games. With that out of the best way, Zen 4 seems like a really strong follow-on to Zen 3. AMD has made enhancements in an important areas, whereas resisting the temptation to bloat core space chasing diminishing returns. The core ought to do a wonderful job in filling out AMD’s CPU portfolio, and I stay up for seeing how AMD follows up on Zen 4 of their future designs.

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