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Designing My Very Personal ASIC with Tiny Tapeout – Tea and Tech Time

Designing My Very Personal ASIC with Tiny Tapeout – Tea and Tech Time

2023-01-25 14:33:46

First, what’s an ASIC? An ASIC is an Software Particular Built-in Circuit which principally signifies that it’s an Built-in Circuit on a single piece of silicon and its use is restricted to a selected utility or perform. An instance could be an ASIC to course of an audio CODEC or run a selected cryptographic perform. However why is creating one so troublesome?

Value! From all of the instrument licensing and the fab prices can attain almost 1 Million {dollars}! That isn’t one thing the conventional maker has readily available. This additionally doesn’t embrace the precise engineering value of designing all of the IP that goes into the chip. So what has modified? A brand new open-source Course of Growth Package from Google and Skywater and the OpenLane ASIC instruments from Efabless was launched. This allowed anybody to get began designing their very own ASICs. However what in regards to the fabrication prices? Nicely, these are nonetheless costly however to not the identical diploma since there at the moment are choices to share designs on the identical silicon wafer being produced. These are known as Shuttles and there’s even a free one primarily based on a lottery system.

Hackaday Supercon Tiny Tapeout Class

Matt Venn instructing the Hackaday Supercon 2022 Tiny-Tapeout Workshop

I had heard about these developments since it’s intently associated to my line of labor FPGA improvement. However didn’t actually have the chance till final yr’s Hackaday Supercon the place I used to be ready to join a workshop introduction to the open ASIC instruments and the Tiny Tapeout mission.

TinyTapeout is an academic mission that makes it simpler and cheaper than ever to get your digital designs manufactured on an actual chip!

The Tiny-Tapeout mission takes one of many spots of the silicon shuttle and additional divides that into smaller designs that construct infrastructure to assist convey up the design and get began.

This workshop was taught by Matt Venn who additionally runs the Zero to ASIC on-line course that does precisely what the identify implies, instructing you the fundamentals Al the way in which by means of utilizing the instruments to design your personal chip.

Zero-to-ASIC Course

Open Supply Silicon Chip

Since we solely had a couple of hours at Supercon there was clearly not sufficient time for the individuals to design every part. However we did undergo the digital logic tutorials in Wokwi. This browser-based software program can be utilized to simulate a wide range of {hardware} however we had been utilizing it to attach up logic gates and flip flops.

Wokwi is a web-based Electronics simulator. You need to use it to simulate Arduino, ESP32, and plenty of different fashionable boards, elements and sensors.

Wokwi Logic Tutorial

However after you have the circuit designed utilizing the Wokwi elements you may submit the design to the Tiny-Tapeout mission by forking their template repo, including the Wokwi ID to the documentation, and working two GitHub actions that run a design guidelines test, then creating the ASIC block.

However what do I need to construct, I couldn’t go too loopy as there’s a area and IO limitation that makes processing a problem.

Tiny-Tapeout Constraints

The design constraints within the Tiny-Tapeout ASIC are fairly limiting when in comparison with the big design area of conventional ASICs however we’re simply beginning so it’s good to have some limitations. First is the IO constraint, we’re restricted to eight enter pins and eight output pins, this consists of any management and clock indicators that our design would possibly want. Subsequent is the realm constraint, every design was lately elevated to 150 x 170 um for Tiny-Tapeout 2. That is roughly sufficient for 1000 logic gates.

My ASIC Design Half 1

I made a decision to tackle an bold design that I may use to check out my digital logic design and sign processing abilities, so I made a decision to strive constructing an FIR filter! An FIR filter is a Finite Impulse Response filter that’s used in every single place in Digital Sign Processing (DSP). They’re used to create low go, excessive go, and bandpass filters performing sign conditioning earlier than different sign processing features.

As a result of area and io constraints, I couldn’t design a really helpful FIR filter nevertheless it was a great train in digital design and stored me eager about finishing the mission by the deadline!

Constructing Blocks

My design methodology was to construct incremental blocks of digital logic that I may then chain collectively into the bigger performance of a filter. It is because I wanted to do a number of math features like including and multiplying.

I made a decision to create a 4-bit 2-tap FIR filter, this suits throughout the unique measurement constraints and takes benefit of the total 8-bit output. This leaves inputs for a clock sign, three choice indicators that we have to permit loading of the filter faucets and testing, after which 4 inputs for faucet and sign knowledge.

Within the Wokwi logic choices, we don’t have an adder block however we do have fundamental and, or, nor, xor, and so on gates. These will be related collectively to make a full adder circuit that takes in 2 bits (and a carry bit) and outputs the sum (and a carry bit) proven within the circuit diagram under.

These adder cases will be chained collectively by means of the carry sign to create the 4-bit adder that we’d like for the filter.

binary-adder-and-subtractor Logic Reference

To create the multiplier logic wanted to multiply the Faucet with the incoming sign I used the adder design with and gates replicating the circuit under.

4-by-4-bit-multiplier Logic Reference

Then in an effort to mix the output from the 2 faucet multiplications I created an 8-bit adder by extending the carry chain of two 4-bit adders.

That’s many of the mathematical features taken care of, however there’s extra to implementing a filter than simply math. We want management logic to accurately feed the mathematical features with knowledge to function on.

For an FIR filter, we’d like a approach to retailer the multiplication faucet weights that affect the kind of filter that we need to course of the incoming knowledge. Which means we’d like our circuit to retailer knowledge, however up till this level now we have solely been utilizing logic gates to course of excessive or low values, how will we make these retailer knowledge?

That is finished utilizing what is usually generally known as a flip-flop proven in its primitive, the place knowledge is loaded into it through an allow sign.

Fortunately we don’t want to copy this logic in Wokwi, as there’s a flip-flop element.

That is fairly good however in an effort to load the faucets one after the other with out overwriting them I made a decision so as to add a modification to knowledge storage by including a second flip-flop and a nor gate on the allow into the primary factor.

So what does this do? it makes the information obtainable on the output depending on the allow sign change so when it goes from excessive to low or low to excessive. this will then be chained with a pulse generator to create a dependable loading mechanism that may be tied to a clock.

Now we additionally have to implement a delay line that feeds every of the faucets with the enter sign knowledge. this may be achieved with only a easy set of flip-flops as we don’t want the complicated loading mechanism.

Registers Logic Reference

After creating the entire digital processing logic I additionally wanted to consider how I used to be going to check the {hardware} performance after I finally obtain my design in {hardware}. For this, I made a decision to multiplex a number of indicators in order that I may simply check the useful blocks within the design just like the multiply operation unbiased of the remainder of the filter.

You possibly can try the design on Wokwi and mess around with it on the hyperlink under

After finishing the entire design I then wanted to create my submission to the Tiny-Tapeout mission. This was finished by forking the GitHub template submission utilizing GitHub actions. The entire course of was detailed in a video on the Tiny-Tapeout mission.

As soon as accomplished it’s best to be capable to see a extremely cool graphic of the ASIC steel layers of the design.

See Also

GDS view of ASIC steel layers

To submit your design to Tiny-Tapeout it’s good to hyperlink your GitHub repo and pay for the choice that you really want. Once I submitted my design it was $100 for a spot on silicon and to obtain a board with the chip on it for testing. If you happen to simply wished your design on the chip it was $20!

My Second ASIC Design Half 2

Fortunately I used to be in a position to get my FIR filter design finished earlier than the unique deadline however as a result of it bought prolonged I began excited about what different issues I may add on since a second design on the identical chip was solely $20 additional.

I workshopped a couple of concepts however sadly, most had been simply not attainable with the present limitations of the design medium. So I made a decision to maintain it easy and create a PRBS generator. PRBS stands for a pseudorandom binary sequence which in easy phrases is a sequence of 1s and 0s that approximate random knowledge. Producing really random sequences may be very troublesome however a PRBS will be generated by a easy LFSR circuit.

An LFSR is a linear suggestions shift register, which is basically only a shift register the place the enter is a linear perform of its earlier state. This suggestions is mostly created by an XOR of the output of calculated factors within the shift register. For extra info on PRBS mills utilizing LFSRs try this nice DigiKey article.

PRBS knowledge will also be used as a approach to test digital communication hyperlinks utilizing a precept of the LFSR. In that, the inverted output of 1 LFSR will be fed into a replica logic and will be checked for errors in that knowledge. So if a communication channel introduces errors attributable to noise the bit error charge will be measured.

As a result of the LFSR is a mathematical perform we will have a number of variants however I made a decision to go together with a easy PRBS15 format, the place there are 15 bits within the shift register. Under is the Wokwi design, the place now we have two LFSRs the place the output is looped again into the enter externally.

This simulation additionally features a logic analyzer so we will plot the output in GTKWave!

From the highest we will see the enter clock on D0, then the PRBS15 output on D1, subsequent is the PRBS15 checker output error on D2, and lastly the PRBS15 checker uncooked output on D3. The checker begins throwing errors at first however as soon as it locks on the error sign stays zero for the whole simulation as there aren’t any errors launched.

You possibly can try this design submission at my different GitHub hyperlink under.

Tiny-Tapeout 2

A bit extra info on Tiny-Tapout 2 which is restricted to the run my designs is on.

Try the total record of designs that went into this Tiny-Tapout run, there’s even a datasheet with descriptions of methods to work together with the designs that each one submissions included! So not solely are you able to run your personal design while you get the chip you may check out the others as properly.

Subsequent Steps

Now that the design has been submitted to the fab we simply have to attend for the chips and the Tiny-Tapeout boards to be delivered. I’ll submit updates after I get my board and see if issues work!

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