European Processor Designed for Use in Area Taped Out
The European Area Company is investigating some ways to spice up computing capabilities in area, and one of many processors it’s backing is near launch.
The area company is a part of a bunch growing an open-source processor known as Occamy, which is predicated on RISC-V. The chip was nearer to completion and is now being assembled after being taped out late final 12 months, researchers stated throughout a presentation eventually month’s Design, Automation and Test in Europe Conference.
The 432-core chip is an fascinating mixture of outdated and new tech, and has been designed utilizing the comparatively new chiplet method. The chiplet design permits the blending and matching of outdated and new applied sciences – similar to analog or digital processors – inside a chip package deal.
Occamy is a low-power chip for AI and high-performance computing workloads. AI workloads right this moment largely depend on accelerators like GPUs and AI cores for coaching and inferencing, and the researchers hope the open-source chip is also utilized in earth-bound AI workloads.
The chip is being developed as a part of the EuPilot program, which is growing homegrown processors to scale back reliance on proprietary x86 and ARM chips. The core Occamy chip improvement is being carried out by researchers at ETH Zürich and College of Bologna.
The European Processor Initiative can be growing sovereign chips for supercomputers, AI, IoT, and autonomous vehicles.
ESA is within the chips as a result of it’ll enable tools in area to carry out on-chip knowledge evaluation. Whereas there is no such thing as a assure that ESA will put the chip in operation, it’s one among many processors being explored for spaceflight computing. NASA has additionally adopted RISC-V chips from Microchip and SiFive to improve its spaceflight computer systems.
The researchers designing the Occamy chip are hoping the chip design can be adopted and reproduced to be used in additional functions.
Occamy is a singular mixture of low-overhead CPU cores, AI accelerators, and reminiscence cores. The chiplet consists of two computing tiles – every with 216 RISC-V cores – with two 16GB HBM2e reminiscence cores. The design additionally consists of 64-bit floating level items for matrix calculations. The cores are linked by a silicon interposer.
The chip has a complete of round 1 billion transistors over 72mm^2, which is about the identical as a quad-core Sandy Bridge chip made by Intel in 2011 (which was 3 times bigger). The RISC-V chip delivers about 0.75 teraflops of FP64 efficiency, or 6 teraflops of FP8 efficiency. The chip doesn’t want cooling followers.
The core RISC-V design has a compact instruction set, and acceleration modules might be tacked on prime of it. The flexibleness permits ESA to design hardened compute modules that don’t break and may stand up to excessive temperatures in area.
Occamy has a light-weight 32-bit CPU core that acts extra as a management chip, and it’s accountable for rerouting duties to the AI cores, that are extensions to the instruction set structure. The HBM2e reminiscence tile was supplied by Micron, and the chip is being manufactured by Globalfoundries on the 12-nanometer low-power course of.
The design intends to assist high-performance and AI workloads by a bare-metal runtime, in line with the slides offered on the DAC convention. It isn’t but clear if the runtime can be at a container stage, or on the bare-metal stage which requires no intervention from the OS. The intent of the researchers is for the chip to be replicated at a low price, and the implementation might rely upon the software program.
The Occamy chip design might be mapped to FPGAs. It may be examined on two AMD Xilinx Virtex UltraScale+ HBM FPGAs, which has HBM reminiscence, or on the Virtex UltraScale+ VCU1525 FPGA.