Intel Meteor Lake Structure Deep Dive

Intel’s Meteor Lake structure for cell PCs will likely be arriving quickly and to say that Meteor Lake is crucial shift in Intel’s design and manufacturing method may very well be an understatement. In truth, Intel has referred to as Meteor Lake the largest architecture shift within the final 40 years, and it’ll affect designs for a decade to come back.

Intel has outlined 4 key pillars for Meteor Lake. First, it’s designed to be probably the most energy environment friendly consumer processor within the firm’s historical past. Second, it will likely be Intel’s first shopper CPU to ship a devoted AI engine at scale. Third, Intel is concentrating on a leap in graphics efficiency together with energy effectivity. Lastly, it will likely be the debut of the Intel 4 course of, a minimum of partially.

Intel Bets On Disaggregation With Meteor Lake

Meteor Lake is the corporate’s first really disaggregated consumer chip, and its improvement has been difficult. Disaggregation implies that reasonably than utilizing a single monolithic die to deal with the CPU cores, built-in GPU, I/O options, and different uncore “stuff,” varied engines are as a substitute damaged out into a number of chiplets that Intel calls Tiles.

That is a horny method for a lot of causes. Dies can solely be made so giant, whereas remaining economically and bodily possible. Present processes are restricted by reticle sizes in the course of the lithography etching, however there’s extra to think about than simply this (kind of) laborious restrict. A bigger die not solely has extra “wasted” area across the edges of a spherical 300mm wafer, however can also be extra more likely to have debilitating defects, and that has a direct destructive influence on yields. Smaller chips let producers extract extra from every wafer, maximizing the potential worth of every.

Breaking apart a design into smaller chiplets has its personal drawbacks, in fact. Packaging it all together turns into much more advanced, irrespective of the way you slice it. If we disregard 3D V-Cache for a second, AMD arranges chiplets round one another on a single PCB for its processors, whereas Intel opts to stack silicon instantly utilizing its Foveros and Embedded Multi-die Interconnect Bridge (EMIB) applied sciences. Foveros and EMIB are related, however distinct superior packaging methods that Intel has been utilizing in some merchandise for a number of years now.

EMIB debuted first in 2017 within the Stratix 10. This was a field-programmable grid array (FPGA) chip, however the expertise has matured into excessive quantity manufacturing and is utilized by Sapphire Rapids today. EMIB makes use of 55um pitch interconnects to mount die atop the embedded silicon bridge.

Foveros permits for active-on-active “3D” stacking with better complexity. Foveros was launched with Lakefield in 2020, the place it allowed Intel to layer a compute die with PoP DRAM on high of a base die that’s then mounted on the package deal substrate.

Meet Meteor Lake’s Tiles

Meteor Lake’s design makes use of 4 distinct tiles driving atop a base tile assembled utilizing Foveros 3D packaging technology. These are the Compute tile, GPU tile, SOC tile, and IO tile respectively, which supplies some perception into the core operate of every. There are definitely some nuances to this although, so lets shortly go over the high-level attributes of every earlier than we dig deeper.

The Compute tile is the place many of the processors cores reside. Most it’s possible you’ll ask? We’ll get to that. The Compute tile options a mixture of the P-cores and E-cores we’re used to from Alder Lake and Raptor Lake, with some microarchitectural enhancements. The Compute tile is constructed utilizing the Intel 4 process node and is definitely the one tile within the system instantly fabbed by Intel.

The GPU tile is subsequent up. As anticipated, this accommodates Intel’s Arc Graphics structure, specifically Xe-LPG. That is fabbed by TSMC on its N5 course of and designed to ship an approximate 2x efficiency per watt enchancment over the twelfth gen Xe graphics. The Graphics tile doesn’t home the Media Engine, although. That has been separated out to reside on the SOC tile, together with the show interfaces.

The SOC tile is the house of all kinds of capabilities throughout two scalable materials. The North aspect options the Community on Chip (NOC) material linking excessive efficiency units whereas the South aspect has an environment friendly PCIe-based IO material, with an IOC bridge linking the 2. Past connectivity and the media/show engines, it additionally homes the NPU AI engine, reminiscence controller, and two particular E-Cores of its personal. The IO tile acts as an extension of the SOC tile’s IO material and each are fabbed utilizing TSMC’s N6 course of.

SOC And IO Tile Particulars

As we dive deeper into the structure, let’s begin with the SOC tile. It sits on the middle of all the things and hyperlinks on to the Compute, Graphics, and IO tiles. In impact, these linkages are the place “cuts” have been made to interrupt out from a standard monolithic die method. If we again up for a second, SOC architectures are deceptively complex, and impacts fab initiated processes and the power to ramp new nodes. Breaking the chip up like this frees the architects to work with IP acceptable manufacturing processes. The disaggregation ensures that Compute Tile of future merchandise, for instance, can shortly ramp to Intel 3 and past whereas the opposite components of the SOC, which can not profit a lot from extra superior course of nodes, can advance at a slower charge.

Meteor Lake’s architectural shifts and design philosophies have been pushed by a number of initiatives. The primary was to implement the NOC material to fulfill the calls for of high-performance units, whereas letting the IO material present environment friendly entry for decrease energy makes use of. To enhance IO effectivity, Intel moved graphics to its personal tile, however stored the media and show blocks with the SOC tile. Lastly, the ability administration system wanted to be scalable, with management over every tile and even subsystems inside the tiles. For example, this permits the PMC for the Compute Tile to be tuned to the variety of P- and E-cores obtainable, whereas the central PMC on the SOC tile is agnostic to the Compute Tile configuration.

The “North” NOC material is a cache-coherent, un-ordered interface spanning throughout the SOC Tile, from the Compute Tile to the Graphics Tile. Inside the SOC tile, it hyperlinks excessive efficiency units just like the reminiscence controller, LP E-Cores, Neural Processing Unit (NPU), and the Media, Imaging, and Show engines. It additionally has an area energy administration unit (P-Unit) for regional management, main to raised effectivity.

The inclusion of LP E-cores on the SOC is an attention-grabbing determination with vital ramifications, significantly for Thread Director. The design permits this pair of cores to stay lively even whereas the Compute Tile is in a low-power mode or shut off solely. Because of this, this creates loads of potential to dramatically enhance Meteor Lake’s effectivity throughout widespread utilization patterns.

The “South” IO material is ordered, however non-coherent and PCIe-based. It’s residence to Wi-Fi and Bluetooth, PCI Categorical connections, Sensing, USB 3/2, Ethernet, the Energy Administration Controller (PMC), and Safety controllers. Intel has damaged out the Silicon Safety Engine from its conventional Converged Safety and Manageability Engine (CSME).

The IO Tile gives further PCI Categorical and USB4/Thunderbolt connectivity utilizing the IO material. The IO Tile’s positioning alongside the Compute Tile is deliberate, as this configuration successfully extends the floor space of the SOC to make outdoors connections much less crowded.

However there may be nonetheless way more to cowl…