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Manta Documentation

Manta Documentation

2024-03-07 18:49:16

Manta is a instrument for transferring information between a number machine and a FPGA over UART or Ethernet. It is primarily meant for debugging and fast prototyping of FPGA designs, however it’s strong sufficient for use as a easy, dependable transport layer.

Manta works by producing plenty of cores which are instantiated within the FPGA design. These permit for a wide range of capabilities, equivalent to studying and writing to registers and reminiscence, or capturing information with a logic analyzer. These cores are operated by the related host machine via both the Manta CLI, or a easy Python API.

Manta is written in Amaranth HDL, and the generated designs could also be used natively in different Amaranth designs, or exported to vendor-agnostic Verilog-2001. All dependencies are cross-platform, so Manta can be utilized on any machine that has a minimum of Python 3.8 or newer put in.

Manta’s capabilities are greatest mirrored in its cores, for which a short description of every is offered beneath:

Logic Analyzer Core

Extra particulars accessible on the full documentation page.

This core captures a timeseries of digital indicators from throughout the FPGA, very similar to a benchtop logic analyzer would. This captures information on the FPGA’s native clock and presents it as a waveform, making it very helpful for debugging logic cycle-by-cycle. This idea is similar to the Xilinx Integrated Logic Analyzer (ILA) and Intel SignalTap utilities.

You might discover this core helpful for:

  • Verifying specification adherence for related {hardware} – as an illustration, you are writing a S/PDIF decoder that works in simulation, however fails in {hardware}. The logic analyzer core can document a cycle-by-cycle seize of what is coming off the cable, letting you confirm that your enter indicators are what you anticipate. Even higher, Manta will allow you to play that seize again in your most popular simulator, letting you feed the very same inputs to your module in simulation and verify your logic.

  • Capturing arbitrary information – you are engaged on a DSP venture, and also you’d prefer to seize some check information out of your onboard ADCs to begin prototyping your sign processing with. Manta will seize that information, and export it for you.

I/O Core

Extra particulars accessible on the full documentation page.

This core presents a sequence of user-accessbile registers to the FPGA material, which can be configured as both inputs or outputs. The worth of an enter register will be learn off the FPGA by the host machine, and the worth of an output register on the FPGA could also be set by the host machine. That is useful for getting small quantities of knowledge into and out of the FPGA, debugging, configuration, or experimentation. This idea is similar to the Xilinx Virtual IO and Intel In-System Sources and Probes instruments.

You might discover this core helpful for:

  • Prototyping designs in Python, and incrementally migrating them to {hardware} – you are engaged on some real-time sign processing, however you wish to prototype it with some pattern information in Numpy earlier than meticulously implementing every part in Verilog.

  • Making dashboards – you’d prefer to get some telemetry out of your current FPGA design and show it properly, however you do not wish to implement an interface, design a packetization scheme, and write a library.

    See Also

Reminiscence Cores

Extra particulars accessible on the full documentation page.

This core creates a two-port block reminiscence on the FPGA, and offers one port to the host machine, and the opposite to your logic on the FPGA. The width and depth of this block reminiscence is configurable, permitting massive chunks of arbitrarily-sized information to be shuffled onto and off of the FPGA by the host machine, by way of the Python API. This allows you to set up a transport layer between the host and FPGA, that treats the info as precisely the way it exists on the FPGA.

You might discover this core helpful for:

  • Shifting information between a number and related FPGA – you are engaged on a cool new machine studying accelerator, however you do not wish to take into consideration tips on how to get coaching information and weights out of TensorFlow, and into your core.

  • Hand-tuning ROMs – you are designing a digital filter for a DSP venture and want to tune it in real-time, otherwise you’re creating a smooth processor and wish to add program code with out rebuilding a bitstream.

About

Manta and its supply code are launched below a GPLv3 license, and it was initially developed as a part of my Master’s Thesis at MIT in 2023, completed below the supervision of Dr. Joe Steinmeyer. The thesis itself is copyrighted by Fischer Moseley (me!), however be at liberty to make use of the next Bibtex if you would like to quote it:

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