Microbenchmarking AMD’s RDNA 3 Graphics Structure – Chips and Cheese

RDNA 3 represents the third iteration of AMD’s RDNA structure, which replaces GCN of their client graphics lineup. At a excessive stage, RDNA 3 goals to massively scale up in comparison with RDNA 2. The cache setup is tweaked in any respect ranges to ship elevated bandwidth. To scale compute throughput past simply including extra WGPs, AMD applied twin challenge functionality for a subset of widespread directions.

On this article, we’re going to do some microbenchmarking on a 7900XTX and take a look at variations in comparison with AMD’s RDNA 2 structure. We’re additionally going to be incorporating outcomes from Nemes’s GPU microbenchmarking suite. Whereas I’ve first rate protection for CPU microbenchmarking, I haven’t been in a position to put almost as a lot time into my OpenCL bsaed checks. Nemes has made wonderful progress on her Vulkan-based GPU take a look at suite, and her take a look at gives higher protection in sure areas.

Reminiscence Latency

Testing cache and reminiscence latency offers us take a look at RDNA 3’s cache and reminiscence setup. Latency testing can also be sophisticated on post-GCN AMD graphics architectures, as a result of the worldwide reminiscence hierarchy will be accessed by way of both the scalar or vector datapaths, which have totally different first stage caches. If the compiler determines {that a} loaded worth is fixed throughout a wavefront, it will probably inform the GPU to make use of the scalar datapath. As a result of the scalar path is used for latency delicate stuff like calculating reminiscence addresses for a load throughout the wavefront, latency is kind of first rate (for a GPU). When accessing world reminiscence AMD makes important use of each the vector and scalar sides. The precise proportion will fluctuate relying on workload, however usually, each are essential.

Let’s begin by wanting on the scalar facet. Like RDNA 2, RDNA 3 has a 16 KB, 4-way set associative scalar cache. Load-to-use latency for this cache is kind of good at 15.4 ns for RDNA 3, and 17.4 ns for RDNA 2. RDNA 3 not less than partially owes its latency benefit to larger clock speeds. Nvidia’s Ada Lovelace has barely higher latency when hitting the SM’s L1, which is spectacular contemplating the scale of Nvidia’s cache. We see 64 KB of L1 cache capability right here, however Ada Lovelace really has a 128 KB block of SRAM that may be flexibly partitioned between L1 and shared reminiscence (LDS) makes use of.

AMD additionally elevated capability within the L1 and L2 mid-level caches, so as to higher deal with the bandwidth calls for from a bigger GPU. RDNA 2 had a 128 KB, 16-way set associative L1 shared throughout a shader array. RDNA 3 doubles capability to 256 KB, whereas sustaining 16-way associativity. L2 cache capability will increase to six MB, in comparison with 4 MB on RDNA 2, whereas additionally sustaining 16-way associativity. Regardless of these capability will increase, RDNA 3 delivers measurable latency enhancements at each L1 and L2.

Nonetheless, RDNA 3’s Infinity Cache regresses considerably. Capability decreases from 128 MB to 96 MB, and latency will increase on the similar time. That’s not stunning, as a result of RDNA 3’s Infinity Cache is applied on separate reminiscence controller dies. But it surely additionally shouldn’t be a giant deal. RDNA 3 will probably be capable of service extra reminiscence accesses with its on-die L2, and never need to hit Infinity Cache as usually.

To scale back reminiscence bandwidth calls for, Nvidia has chosen to massively scale up the L2 as a substitute of including one other stage of cache. That pushes up L2 latency a bit in comparison with AMD’s latest GPUs, however does give Ada Lovelace superior latency traits for reminiscence footprints going into the dozens-of-megabytes vary. The RTX 4090’s L2 has 72 MB of capability, lower down from the 96 MB of SRAM bodily current on the die.

VRAM latency is up barely on RDNA 3 in comparison with RDNA 2. Nvidia holds a bonus in that space, partially as a result of AMD incurs further latency after they verify an additional stage of cache on the way in which to DRAM.

Vector Latency

After all, latency for the vector path is essential too, so I’ve modified the take a look at to stop the compiler from figuring out that the loaded worth will likely be fixed throughout the wavefront. Particulars are in another article. From the vector facet, AMD sees elevated latency, however vector accesses must be much less latency delicate. The vector cache’s design additionally performs a job – it’s 32-way set associative on each RDNA 2 and RDNA 3, in comparison with the 4-way scalar cache. Checking 32 tags on a lookup might be going to incur larger latency than checking 4.

Nonetheless, RDNA 3 manages to lower L0 vector cache latency in comparison with RDNA 2, whereas doubling capability to 32 KB per CU.

Additional down the cache hierarchy, latency traits principally mirror that of the scalar facet, although after all absolute latencies are larger. RDNA 2’s VRAM latency benefit can also be diminished once we take a look at from the vector facet. The 2 architectures find yourself a couple of nanoseconds off on the 1 GB take a look at measurement, which is mainly nothing.

Reminiscence Bandwidth

The Radeon 7900 XTX has extra WGPs than the 6900 XT. On the similar time, every WGP has extra compute throughput on faucet, so the reminiscence subsystem must be beefed as much as feed them. RDNA 3 subsequently sees huge bandwidth will increase at each stage within the reminiscence subsystem. The L1 and L2 caches see particularly spectacular features, with bandwidth roughly doubling in comparison with RDNA 2 despite the fact that their capability can also be elevated.

Infinity Cache bandwidth additionally sees a big enhance. Utilizing a pure learn entry sample, we weren’t in a position to get the complete 2.7x bandwidth enhance that must be theoretically potential. Nonetheless, a 1.8x bandwidth enhance is nothing to joke about. The bandwidth benefit is spectacular contemplating the Infinity Cache is bodily applied on totally different chiplets, whereas RDNA 2 saved the Infinity Cache on-die.

AMD has additionally outfitted the 7900XTX with a a lot bigger GDDR6 setup, giving it much more bandwidth than the 6900XT. The truth is, its VRAM bandwidth is lots nearer to GA102’s. That in all probability allowed AMD to keep up excessive efficiency whereas lowering the quantity of final stage cache, permitting for smaller reminiscence controller dies.

Bandwidth at Decrease Occupancy

Trendy GPUs are constructed to reap the benefits of huge quantities of specific parallelism. However some workloads don’t have sufficient parallelism to fill all accessible compute items. Vertex shaders, I’m you. Nemes’s take a look at suite at the moment doesn’t get away outcomes for decrease workgroup counts, so I’m utilizing OpenCL outcomes right here.

Let’s begin with bandwidth for a single workgroup. Operating a single workgroup limits us to a single WGP on AMD, or a SM on Nvidia architectures. That’s the closest we will get to single core bandwidth on a CPU. Like single core bandwidth on a CPU, such a take a look at isn’t notably consultant of any actual world workload. But it surely does give us a glance into the reminiscence hierarchy from a single compute unit’s perspective.

Once more, we will see RDNA 3’s bigger on-die caches. From a single WGP’s viewpoint, all three of these cache ranges supply elevated bandwidth. Nvidia has a really massive and quick first-level cache, however after that AMD has a bonus so long as it will probably serve accesses from L1 or L2.

From Infinity Cache, RDNA 3 has a tougher time, probably as a result of a single WGP didn’t get sufficient of a rise in reminiscence stage parallelism capabilities to soak up the rise in Infinity Cache latency. The truth is, Infinity Cache bandwidth for one WGP has decreased in comparison with the place it was in RDNA 2. The scenario flips once more once we hit VRAM, the place RDNA 3 pulls forward.

Bandwidth Scaling

Shared caches are good as a result of their capability can be utilized extra effectively. As an alternative of duplicating shared information throughout a number of non-public caches, a shared cache can retailer the info as soon as and repair requests for it coming from a number of compute items. Nonetheless, a shared cache is difficult to implement, as a result of it has to have the ability to deal with the bandwidth calls for of all of its purchasers.

We’re going to begin with L2 bandwidth as a result of L0 and L1 bandwidth scale nearly linearly. L2 scaling is way tougher to drag off as a result of a single 6 MB L2 cache has to service all 48 WGPs on the GPU. With that in thoughts, RDNA 3’s L2 does an excellent job with scaling to satisfy the bandwidth calls for of all these WGPs. As WGP rely will increase, RDNA 3’s L2 bandwidth begins to drag away from RDNA 2’s.

Each AMD architectures are in a position to present extra L2 bandwidth to matched workgroup counts, in comparison with Nvidia’s Ada Lovelace. Nonetheless, the RTX 4090 has bigger first-level caches that ought to scale back L2 site visitors. Ada Lovelace’s L2 additionally serves a barely totally different position, doubling as an Infinity Cache of types. Contemplating its very massive capability, Nvidia’s L2 does extraordinarily nicely. If we examine towards RDNA 3’s Infinity Cache, which has related capability, Ada’s L2 maintains related bandwidth at low occupancy. When all of Ada’s SMs come into play, Nvidia enjoys a considerable bandwidth benefit. After all, AMD’s Infinity Cache doesn’t want to offer as a lot bandwidth as a result of the L2 cache will usually soak up an honest proportion of L1 miss site visitors.

In comparison with RDNA 2, RDNA 3’s Infinity Cache is a bit slower to ramp up, and is at a drawback with lower than half of its WGPs loaded. However when workloads scale to fill all of the WGPs, RDNA 3’s Infinity Cache exhibits a considerable bandwidth benefit over RDNA 2’s.

From VRAM, each AMD architectures take pleasure in superb bandwidth at low occupancy. RDNA 3 begins with a small benefit that will get bigger as extra WGPs come into play. From one other perspective, RDNA 2’s 256-bit GDDR6 setup might be saturated with simply 10 WGPs. RDNA 3’s larger VRAM subsystem can feed extra WGPs demanding full bandwidth. Nvidia has extra bother with VRAM bandwidth if just a few SMs are loaded, however takes a lead at larger occupancy.

Native Reminiscence Latency

Along with the common world reminiscence hierarchy, GPUs even have quick scratchpad reminiscence. OpenCL calls this native reminiscence. On AMD GPUs, the corresponding construction known as the Native Knowledge Share (LDS). Nvidia GPUs name this Shared Reminiscence. Not like caches, software program has to explicitly allocate and handle native reminiscence capability. As soon as information is within the LDS, software program can count on assured excessive bandwidth and low latency entry to that information.

Like prior RDNA generations, every RDNA 3 WGP will get a 128 KB LDS. The LDS is internally constructed with two 64 KB blocks, every affiliated with one CU within the WGP. Every 64 KB block incorporates 32 banks, every of which might deal with a 32-bit broad entry. That makes it potential for the LDS to service a wavefront-wide load each cycle. We don’t at the moment have a take a look at for LDS bandwidth, however RDNA 3 seems to have a really low latency LDS.

RDNA 3 makes a large enchancment in LDS latency, because of a mixture of architectural enhancements and better clock speeds. Nvidia loved a slight native reminiscence latency lead over AMD’s architectures, however RDNA 3 modifications that. Low LDS latency might be very useful when RDNA 3 is coping with raytracing, as a result of the LDS is used to retailer the BVH traversal stack.

For comparability, RDNA 2’s LDS had about the identical load-to-use latency as its scalar cache. It was nonetheless very helpful as a result of it might get information into vector registers lots quicker than was potential from the L0 vector cache. I checked the compiled code for this take a look at, and it’s utilizing vector registers despite the fact that all however one thread within the workgroup is masked off.

WGP Compute Traits

In comparison with RDNA 2, RDNA 3 clearly has a big benefit in compute throughput. In spite of everything, it has a better WGP rely. However potential will increase in compute throughput transcend that, as a result of RDNA 3’s SIMDs acquire a restricted twin challenge functionality. Sure widespread operations will be packaged right into a single VOPD (vector operation, twin) instruction in wave32 mode. In wave64 mode, the SIMD will naturally attempt to begin executing a 64-wide wavefront over a single cycle, supplied the instruction will be twin issued.

A RDNA 3 VOPD instruction is encoded in eight bytes, and helps two sources and one vacation spot for every of the 2 operations. That excludes operations that require three inputs, just like the generic fused multiply add operation. Twin challenge alternatives are additional restricted by accessible execution items, information dependencies, and register file bandwidth.

Operands in the identical place can’t learn from the identical register financial institution. Earlier we speculated that this was a limitation with dealing with financial institution conflicts. Nonetheless, AMD’s ISA guide clarifies that every financial institution really has a register cache with three learn ports, every of which is tied to an operand place. Two reads from the identical financial institution in the identical supply place would oversubscribe the register cache ports. One other limitation applies to the vacation spot registers, which might’t be each even or each odd.

On this take a look at, we’re working a single workgroup to maintain the take a look at native to a WGP. As a result of enhance conduct is kind of variable on latest GPUs, we’re locking clocks to 1 GHz to drill down on per-clock conduct.

Sadly, testing by way of OpenCL is troublesome as a result of we’re counting on the compiler to seek out twin challenge alternatives. We solely see convincing twin challenge conduct with FP32 provides, the place the compiler emitted v_dual_add_f32 directions. The blended INT32 and FP32 addition take a look at noticed some profit as a result of the FP32 provides had been twin issued, however couldn’t generate VOPD directions for INT32 attributable to an absence of VOPD directions for INT32 operations. Fused multiply add, which is used to calculate a GPU’s headline TFLOPs quantity, noticed only a few twin challenge directions emitted. Each architectures can execute 16-bit operations at double price, although that’s unrelated to RDNA 3’s new twin challenge functionality. Fairly, 16-bit directions profit from a single operation issued in packed-math mode. In different main classes, throughput stays largely much like RDNA 2.

I’m guessing RDNA 3’s twin challenge mode may have restricted affect. It depends closely on the compiler to seek out VOPD potentialities, and compilers are frustratingly silly at seeing quite simple optimizations. For instance, the FMA take a look at above makes use of one variable for 2 of the inputs, which ought to make it potential for the compiler to satisfy twin challenge constraints. However clearly, the compiler didn’t make it occur. We additionally examined with clpeak, and see related conduct there. Even when the compiler is ready to emit VOPD directions, efficiency will solely enhance if compute throughput is a bottleneck, slightly than reminiscence efficiency.

Then again, VOPD does go away potential for enchancment. AMD can optimize video games by changing recognized shaders with hand-optimized meeting as a substitute of counting on compiler code technology. People will likely be significantly better at seeing twin challenge alternatives than a compiler can ever hope to. Wave64 mode is one other alternative. On RDNA 2, AMD appears to compile numerous pixel shaders all the way down to wave64 mode, the place twin challenge can occur with none scheduling or register allocation smarts from the compiler.

It’ll be attention-grabbing to see how RDNA 3 performs as soon as AMD has extra time to optimize for the structure, however they’re undoubtedly justified in not promoting VOPD twin challenge functionality as further shaders. Sometimes, GPU producers use shader rely to explain what number of FP32 operations their GPUs can full per cycle. In concept, VOPD would double FP32 throughput per WGP with little or no {hardware} overhead moreover the additional execution items. But it surely does so by pushing heavy scheduling duty to the compiler. AMD might be conscious that compiler expertise is less than the duty, and won’t get there anytime quickly.

By way of instruction latency, RDNA 3 is much like prior RDNA architectures. Widespread FP operations execute with 5 cycle latency. Nvidia has a slight edge right here, and is ready to execute widespread operations with 4 cycle latency.

Since Turing, Nvidia additionally achieves superb integer multiplication efficiency. Integer multiplication seems to be extraordinarily uncommon in shader code, and AMD doesn’t appear to have optimized for it. 32-bit integer multiplication executes at round 1 / 4 of FP32 price, and latency is fairly excessive too.

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Full GPU Throughput – Vulkan

Right here, we’re utilizing Nemes’s GPU benchmark suite to check full GPU throughput, which takes into consideration enhance clocks with all WGPs energetic. RDNA 3 achieves larger throughput through VOPD directions, larger WGP rely, and better clock speeds. Surprisingly, AMD’s compiler may be very keen to remodel Nemes’s take a look at code sequence into VOPD directions.

The result’s a large enhance in FP32 throughput. FP16 sees a smaller throughput enhance as a result of RDNA 2 is ready to use packed FP16 execution, with directions like v_pk_add_f16. These directions interpret every 32-bit register as two 16-bit parts, doubling throughput. RDNA 3 does the identical, however just isn’t in a position to twin challenge such packed directions. Curiously, RDNA 3 really regresses in FP64 throughput. We already noticed a touch of this earlier with OpenCL, the place one RDNA 2 WGP might execute eight FP64 operations per cycle. RDNA 3 cuts throughput in half, which means a WGP can do 4 FP64 operations – in all probability one per SIMD, per cycle.

Throughput for particular operations is decrease on each GPUs. Reciprocal is commonly used as a option to keep away from costly division operations, and that runs at quarter price on each architectures. Divide is even slower, and doing modular arithmetic on integer operations is about as gradual as doing FP64.

Now, lets speak about that 123TFLOP FP16 quantity that AMD claims. Whereas that is technically right, there are important limitations on this quantity. Trying on the RDNA3 ISA documentation, there is just one VOPD instruction that may twin challenge packed FP16 directions together with one other that may work with packed BF16 numbers.

Which means the headline 123TF FP16 quantity will solely be seen in very restricted situations, primarily in AI and ML workloads though gaming has began to make use of FP16 extra usually.

PCIe Hyperlink

The Radeon 7900 XTX connects to the host through a PCIe 4.0 x16 hyperlink. Like RDNA 2, AMD’s new graphics structure performs very nicely when shifting information to the GPU, particularly in reasonably sized blocks. Switch price is decrease when getting information off the GPU.

Nvidia lands someplace within the center, with first rate switch speeds throughout all copy sizes and instructions. At massive copy sizes, Nvidia appears to have an edge in PCIe switch bandwidth over AMD.

Kernel Launch Latency

Right here, we’re utilizing clpeak to estimate how lengthy it takes for a GPU to launch a kernel and report its completion. Clpeak does this by submitting a really tiny quantity of labor to the GPU and testing how lengthy it takes to finish.

Outcomes appear to fluctuate fairly a bit, and we will’t match platforms with our testing mannequin. Nonetheless, we will inform that there’s nothing out of the atypical with RDNA 3. Nvidia may need barely quicker kernel launches on their GPUs, however since we couldn’t match platforms, it’ll be arduous to attract any conclusions.

Last Phrases

AMD’s RDNA 2 structure introduced the corporate’s GPUs inside putting vary of Nvidia’s greatest, marking one other occasion during which AMD lands inside putting distance of Nvidia’s highest finish playing cards. RDNA 3 seems to hold that ahead by scaling up RDNA 2, whereas introducing architectural enhancements geared toward rising efficiency past simply including WGPs. AMD employs a multi-pronged technique in pursuit of that purpose.

On the bodily implementation facet, AMD moved to TSMC’s extra trendy 5 nm course of node. 5 nm permits for larger transistor density, and enhancements to the WGP with out bloating space. So, the WGP will get elevated register file measurement and twin challenge functionality. Chiplet expertise permits for a smaller principal 5 nm die, by shifting Infinity Cache and reminiscence controllers onto separate dies. That helps allow a better bandwidth VRAM setup through the use of much less space on the graphics die to implement VRAM connectivity.

Increased bandwidth is vital to feeding a bigger GPU, and AMD goes past VRAM bandwidth. Caches bandwidth will increase at each stage. AMD has additionally elevated capability for on-die caches, as a result of off-die accesses are extra energy hungry even with an interposer between dies. Even with a chiplet setup, AMD wants to maximise space effectivity, and twin challenge is a superb instance of that. VOPD directions enable AMD so as to add further execution items for the most typical operations, however with little or no further overhead in different places. AMD additionally elevated vector register file capability, which ought to assist enhance occupancy. And, they dramatically diminished LDS latency. Raytracing looks like an apparent beneficiary of that change.

The result’s a GPU that performs very carefully to Nvidia’s RTX 4080. In keeping with Hardware Unboxed, the 7900 XTX is 1% slower at 1440p, and 1% quicker at 4K. As an alternative of utilizing a really massive WGP/SM rely, AMD achieved their efficiency by enhancing per-WGP throughput. In addition they targeted on protecting the WGPs fed with a extra refined reminiscence hierarchy. Whole final stage cache capability drops in comparison with the earlier technology, as a result of the 384-bit reminiscence bus means RDNA 3 doesn’t want as excessive of a cache hitrate to keep away from bandwidth bottlenecks.

AMD and Nvidia thus make totally different tradeoffs to achieve the identical efficiency stage. A chiplet setup helps AMD use much less die space in a number one course of node than Nvidia, by placing their cache and reminiscence controllers on separate 6 nm dies. In alternate, AMD has to pay for a costlier packaging answer, as a result of plain on-package traces would do poorly at dealing with the excessive bandwidth necessities of a GPU.

Nvidia places every part on a single bigger die on a leading edge 4 nm node. That leaves the 4080 with much less VRAM bandwidth and fewer cache than the 7900 XTX. Their transistor density is technically decrease than AMD’s, however that’s as a result of Nvidia’s larger SM rely means they’ve extra management logic in comparison with register recordsdata and FMA items. Fewer execution items per SM means Ada Lovelace may have a better time protecting these execution items fed. Nvidia additionally has a bonus with their easier cache hierarchy, which nonetheless gives an honest quantity of caching capability.

In any case, it’s nice to see AMD and Nvidia persevering with to compete face to face after years of Nvidia having an unquestioned lead. Hopefully, that’ll result in decrease GPU costs sooner or later, in addition to extra innovation from either side.

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