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Reverse engineering the Intel 386 processor’s register cell

Reverse engineering the Intel 386 processor’s register cell

2023-11-09 11:11:56

The groundbreaking Intel 386 processor (1985) was the primary 32-bit processor within the x86 line.
It has quite a few inside registers: general-purpose registers, index registers, section selectors, and
extra specialised registers.
On this weblog publish, I take a look at the silicon die of the 386 and clarify how a few of these registers are
applied on the transistor stage.
The registers that I examined are applied as static RAM, with every bit saved in a standard 8-transistor circuit, referred to as “8T”.
Learning this circuit exhibits the fascinating format methods that Intel used to squeeze two storage cells collectively to attenuate the area they require.

The diagram beneath exhibits the interior construction of the 386. I’ve marked the related registers with three pink
containers. Two units of registers are within the section descriptor cache, presumably holding cache entries, and one set is on the backside of
the information path. Among the registers on the backside are 32 bits vast, whereas others are half as vast and
maintain 16 bits. (Extra registers with completely different circuits, however I
will not focus on them on this publish.)

The 386 with the main functional blocks labeled. Click this image (or any other) for a larger version. I created this image using a die photo from Antoine Bercovici.

The 386 with the principle purposeful blocks labeled. Click on this picture (or every other) for a bigger model. I created this picture utilizing a die photograph from Antoine Bercovici.

The 6T and 8T static RAM cells

First, I am going to clarify how a 6T or 8T static cell holds a bit.
The fundamental thought behind a static RAM cell is to attach two inverters right into a loop.
This circuit can be steady, with one inverter on and one inverter off, and every inverter supporting the opposite.
Relying on which inverter is on,
the circuit shops a 0 or a 1.

Two inverters in a loop can store a 0 or a 1.

Two inverters in a loop can retailer a 0 or a 1.

To put in writing a brand new worth into the circuit, two indicators are fed in, forcing the inverters to the specified new values.
One inverter receives the brand new bit worth, whereas the opposite inverter receives the complemented bit worth.
This may increasingly seem to be a brute-force approach to replace the bit, but it surely works.
The trick is that the inverters within the cell are small and weak, whereas the enter indicators are greater present,
in a position to overpower the inverters.1
The write knowledge strains (known as bitlines) are linked to the inverters by move transistors.2 When the move transistors are on, the
indicators on the write strains can move by way of to the inverters. However when the move transistors are off, the
inverters are remoted from the write strains.
Thus, the write management sign allows writing a brand new worth to the inverters.
(This sign is named a wordline because it controls entry to a phrase of storage.)
Since every inverter consists of two transistors7, the circuit beneath consists of six transistors,
forming the 6T storage cell.

Adding pass transistor so the cell can be written.

Including move transistor so the cell might be written.

The 6T cell makes use of the identical bitlines for studying and writing.
Including two transistors creates the 8T circuit, which has the benefit that you could learn one register
and write to a different register on the identical time. (I.e. the register file is two-ported.)
Within the 8T cell beneath, two further transistors (G and H) are used for studying.
Transistor G buffers the cell’s worth; it activates if the inverter output is excessive, pulling the learn output bitline low.3
Transistor H is a move transistor that blocks this sign till a learn is carried out on this register;
it’s managed by a learn wordline.

Schematic of a storage cell. Each transistor is labeled with a letter.

Schematic of a storage cell. Every transistor is labeled with a letter.

To type registers (or reminiscence), a grid is constructed from these cells.
Every row corresponds to a register, whereas every column corresponds to a bit place.
The horizontal strains are the wordlines, choosing which phrase to entry, whereas the
vertical strains are the bitlines, passing bits in or out of the registers.
For a write, the vertical bitlines present the 32 bits (together with their enhances).
For a learn, the vertical bitlines obtain the 32 bits from the register.
A wordline is activated to learn or write the chosen register.

Static memory cells (8T) organized into a grid.

Static reminiscence cells (8T) organized right into a grid.

Silicon circuits within the 386

Earlier than exhibiting the format of the circuit on the die, I ought to give a little bit of background on the know-how used
to assemble the 386.
The 386 was constructed with CMOS know-how, with NMOS and PMOS transistors working collectively, an advance over the
earlier x86 chips that had been constructed with NMOS transistors.
Intel known as this CMOS know-how CHMOS-III (complementary high-performance metal-oxide-silicon), with 1.5 µm options.
Whereas Intel’s earlier chips had a single steel layer, CHMOS-III offered two steel layers, making sign
routing a lot simpler.

As a result of CMOS makes use of each NMOS and PMOS transistors, fabrication is extra sophisticated.
In an MOS built-in circuit, a transistor is fashioned the place a polysilicon wire crosses energetic silicon,
creating the transistor’s gate.
A PMOS transistor is constructed instantly on the silicon substrate (which is N-doped).
Nevertheless, an NMOS transistor is the alternative, requiring a P-doped substrate.
That is created by forming a P effectively, a area
of P-doped silicon that holds NMOS transistors.
Every P effectively should be linked to floor; that is completed by connecting floor to specially-doped areas of the P effectively, known as “effectively faucets”`.

The diagram beneath exhibits a cross-section by way of two transistors, exhibiting the layers of the chip.
There are 4 vital layers: silicon (which has some areas doped to type energetic
silicon), polysilicon for wiring and transistors, and the 2 steel layers.
On the backside is the silicon, with P or N doping; word the P-well for the NMOS transistor on the left.
Subsequent is the polysilicon layer.
On the high are the 2 layers of steel, named M1 and M2.
Conceptually, the chip is constructed from flat layers, however the layers have a three-dimensional
construction influenced by the layers beneath.
The layers are separated by silicon dioxide (“ox”) or silicon oxynitride4; the
oxynitride underneath M2 brought on me appreciable problem.

A cross-section of circuitry formed with the CHMOS-III process. From A double layer metal CHMOS III technology.

The picture beneath exhibits how circuitry seems on the die;5
I eliminated the steel layers to indicate the silicon and polysilicon that type transistors.
(As can be described beneath, this picture exhibits two static cells, holding two bits.)
The pinkish and darkish areas are energetic silicon, doped to participate within the circuits, whereas the “background” silicon
might be ignored.
The inexperienced strains are polysilicon strains on high of the silicon.
Transistors are crucial characteristic right here: a transistor gate is fashioned when polysilicon crosses energetic
silicon, with the supply and drain on both aspect.
The higher a part of the picture has PMOS transistors, whereas the decrease a part of the picture has the P effectively that holds
NMOS transistors. (The effectively itself just isn’t seen.)
In whole, the picture exhibits 4 PMOS transistors and 12 NMOS transistors.
On the backside, the effectively faucets join the P effectively to floor.
Though the steel has been eliminated, the contacts between the decrease steel layer (M1) and the silicon or
polysilicon are seen as faint circles.

A (heavily edited) closeup of the die.

A (closely edited) closeup of the die.

Register format within the 386

Subsequent, I am going to clarify the format of those cells within the 386.
To extend the circuit density, two cells are put side-by-side, with a mirrored format.
On this means, every row holds two interleaved registers.6
The schematic beneath exhibits the association of the paired cells, matching the die picture above.
Transistors A and B type the primary inverter,7 whereas transistors C and D type the second
Go transistors E and F enable the bitlines to write down the cell.
For studying, transistor G amplifies the sign whereas move transistor H connects the chosen bit to the

Schematic of two static cells in the 386. The schematic approximately matches the physical layout.

Schematic of two static cells within the 386. The schematic roughly matches the bodily format.

The left and proper sides are roughly mirror pictures, with separate learn and write management strains for
every half.
As a result of the management strains for the left and proper sides are in numerous positions, the 2 sides have
some format variations, specifically, the bulging loop on the precise.
Mirroring the cells will increase the density because the bitlines might be shared by the cells.

The diagram beneath exhibits the varied parts on the die,
labeled to match the schematic above.
I’ve drawn the decrease M1 steel wiring in blue, however omitted the M2 wiring (horizontal management strains, energy, and floor). “Learn crossover” signifies the connection from the learn output on the left to the bitline on the precise.
Black circles point out vias between M1 and M2, inexperienced circles point out contacts between silicon and M1, and
reddish circles point out contacts between polysilicon and M1.

The layout of two static cells. The M1 metal layer is drawn in blue; the horizontal M2 lines are not shown.

The format of two static cells. The M1 steel layer is drawn in blue; the horizontal M2 strains aren’t proven.

See Also

Yet one more complication is that alternating registers (i.e. rows) are mirrored vertically, as proven beneath.
This permits one horizontal energy line to feed two rows, and equally for a horizontal floor line.
This cuts the variety of energy/floor strains in half, making the format extra environment friendly.

Multiple storage cells.

A number of storage cells.

Having two layers of steel makes the circuitry significantly harder to reverse engineer. The
photograph beneath (left) exhibits one of many static RAM cells because it seems underneath the microscope.
Though the construction of the steel layers is seen within the {photograph}, there’s loads of ambiguity.
It’s tough to tell apart the 2 layers of steel. Furthermore, the steel utterly hides the
polysilicon layer, to not point out the underlying silicon.
The big black circles are vias between the 2 steel layers.
The smaller faint circles are contacts between a steel layer and the underlying silicon or polysilicon.

One cell as it appears on the die, with a diagram of the upper (M2) and lower (M1) metal layers.

One cell because it seems on the die, with a diagram of the higher (M2) and decrease (M1) steel layers.

With some effort, I made up my mind the steel layers, which I present on the precise:
M2 (higher) and M1 (decrease).
By evaluating the left and proper pictures, you possibly can see how the construction of the steel layers is considerably seen.
I take advantage of black circles to
point out vias between the layers, inexperienced circles point out contacts between M1 and silicon, and pink circles point out
contacts between M1 and polysilicon.
Notice that each steel layers are packed as tightly as potential.
The format of this circuit was extremely optimized to attenuate the realm.
It’s fascinating to notice that lowering the scale of the transistors would not assist with this circuit, since
the scale is restricted by the steel density.
This illustrates {that a} fabrication course of should stability the scale of the steel options, polysilicon options,
and silicon options since over-optimizing one will not assist the general chip density.

The photograph beneath exhibits the underside of the register file.
The “notch” makes the registers on the very backside half-width:
4 half-width rows similar to eight 16-bit registers.
Since there are six 16-bit section registers within the 386, I believe these are the section registers and
two thriller registers.

The bottom of the register file.

The underside of the register file.

I have not been in a position to decide which registers within the 386 correspond to the opposite registers on the die.
Within the section descriptor circuitry, there are two rows of register cells with ten extra rows beneath,
similar to 24 32-bit registers. These are presumably section descriptors.
On the backside of the datapath, there are 10 32-bit registers with the T8 circuit.
The 386’s programmer-visible registers encompass eight general-purpose 32-bit registers (EAX, and many others.).
The 386 has varied management registers, check registers, and segmentation registers8 which are
not well-known.
The 8086 has just a few registers for inside use that are not seen to the programmer, so the 386 presumably
has much more invisible registers.
At this level, I can not slim down the performance.

It is fascinating to look at how registers are applied in an actual processor.
There are many descriptions of the 8T static cell circuit, but it surely seems that the bodily implementation
is a sophisticated than the theoretical description.
Intel put loads of effort into optimizing this circuit, leading to a dense block of circuitry.
By mirroring cells horizontally and vertically, the density might be elevated additional.

Reverse engineering one small circuit of the 386 turned out to be fairly tough, so I do not plan to do
a whole reverse engineering.
The principle problem is the 2 layers of steel are onerous to untangle.
Furthermore, I misplaced a lot of the polysilicon when eradicating the steel.
Lastly, it’s onerous to attract diagrams with 4 layers with out the diagram turning into a multitude,
however hopefully the diagrams made sense.

I plan to write down extra in regards to the 386, so
observe me on Twitter @kenshirriff or RSS for updates.
I am additionally on Mastodon often as @[email protected].

Notes and references

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