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Second IC :) – Sam Zeloof

Second IC :) – Sam Zeloof

2023-04-24 02:20:29

Selfmade 1000+ transistor array chip 

In 2018 I made the first lithographically fabricated integrated circuits in my storage fab. I used to be a senior in highschool once I made the Z1 amplifier, and now I’m a senior in faculty so there are some lengthy overdue enhancements to the beginner silicon course of.
The Z1 had 6 transistors and was an ideal take a look at chip to develop all of the processes and tools. The Z2 has 100 transistors on a 10µm polysilicon gate course of – similar know-how as Intel’s first processor. My chip is a straightforward 10×10 array of transistors to check, characterize, and tweak the method however this can be a large step nearer to extra superior DIY pc chips. The Intel 4004 has 2,200 transistors and I’ve now made 1,200 on the identical piece of silicon.

Screen Shot 2021-08-12 at 4.28.35 PM

Only half joking
Solely half joking

Beforehand, I made chips with a metal gate process. The aluminum gate has a big work operate distinction with the silicon channel beneath it which ends up in a excessive threshold voltage (>10V). I used these metallic gate transistors in a number of enjoyable initiatives like a guitar distortion pedal and a ring oscillator LED blinker however each of those required one or two 9V batteries to run the circuit because of excessive Vth. By switching to a polysilicon gate course of, I get a ton of efficiency advantages (self aligned gate means decrease overlap capacitances) together with a a lot decrease Vth which makes these chips appropriate with 2.5V and three.3V logic ranges. The brand new FETs have wonderful traits:

NMOS Electrical Properties:
Vth             = 1.1 V
Vgs MAX         = 8 V
Cgs             = <0.9 pF
Rise/fall time  = <10 ns
On/off ratio    = 4.3e6
Leakage present = 932 pA (Vds=2.5V)

I used to be notably shocked by the tremendous low leakage present. This worth goes up about 100x in ambient room lighting.

Now we all know that it’s attainable to make actually good transistors with impure chemical compounds, no cleanroom, and home made tools. After all, yield and course of repeatability are diminished. I’ll do extra testing to gather knowledge on the statistics and variability of FET properties nevertheless it’s trying good!


The chip is small, about one quarter the die space of my earlier ICs (2.4mm^2) which makes it onerous to probe. There’s a easy 10×10 array of N-channel FETs on every chip which is able to give me quite a lot of characterization knowledge. Because it’s such a easy design, I used to be in a position to lay it out utilizing Photoshop. Columns of 10 transistors share a standard gate connection and every row is strung collectively in sequence with adjoining transistors sharing a supply/drain terminal. It’s just like NAND flash however I solely did this to hold the metallic pads giant sufficient so I can fairly probe them, if each FET had 3 pads for itself they’d be too small.

It’s onerous to convey the joy of seeing a very good FET curve displayed on the curve tracer after dipping a shard of rock into chemical compounds all day.

A single 10µm NMOS transistor may be see beneath, with slight misalignment within the metallic layer (a part of the left contact is uncovered). Purple define is polycrystalline silicon, blue is the supply/drain.

To this point I’ve made an opamp (Z1) and a memory-like array (Z2). Extra fascinating circuits are positively attainable even with this low transistor density. The method wants some tweaking however now that I’m in a position to persistently make good high quality transistors I ought to be capable of design extra advanced digital and analog circuits. Testing every chip may be very tedious so I’m making an attempt to automate the method and I’ll submit extra knowledge then. I’ve made 15 chips (1,500 transistors) and know there’s at the least one utterly useful chip and at the least two “largely useful”, which means ~80% of the transistors work as a substitute of 100%. No correct yield knowledge but. The commonest defect is a drain or supply shorted to the majority silicon channel, not a leaky or shorted gate like on my Z1 course of.

Profilometer scan of gate
Profilometer scan of gate layer (y axis in angstrom, x axis is micron)

I mentioned earlier than that the gate was made out of aluminum and now it’s silicon which makes the chips work loads higher. Silicon is available in three varieties that we care about: amorphous, polycrystalline, and monocrystalline. From left to proper, these turn into extra electrically conductive but in addition a lot more durable to deposit. In truth, monocrystalline Si can’t be deposited, you possibly can solely develop it involved with one other mono-Si layer as a seed (epitaxy). For the reason that gate should be deposited on prime of an insulating dielectric, poly is one of the best we are able to do. We are able to closely dope the polysilicon anyway to make it extra conductive.

A typical self-aligned polysilicon gate course of requires silane, a poisonous and explosive fuel, to deposit polycrystalline silicon layers. It might even be attainable by sputtering or evaporating amorphous silicon and annealing with a laser. A serious theme of this DIY silicon course of is to bypass costly, tough, or harmful steps. So, I got here up with a modified course of move. It’s a variation on the usual self-aligned strategies to permit doping through excessive temperature diffusion somewhat than ion implantation. The impact is that I’m in a position to purchase a silicon wafer with the polysilicon already deposited on it from the manufacturing unit and sample it to make transistors as a substitute of placing my very own polysilicon down midway by way of the method. This can be a good brief time period workaround however it will be finest to design a polysilicon deposition course of utilizing the laser anneal methodology talked about above.

Wafers can be found with every kind of supplies deposited on them already, so I simply needed to discover one with a skinny layer of SiO2 (gate oxide, ~10nm) adopted by a thicker polysilicon (300nm). I discovered quite a lot of 25 200mm (EPI, prime, [1-0-0], p-type) wafers on eBay for $45 which is actually a lifetime provide, so e-mail me if you would like one. The gate oxide is probably the most fragile layer and requires probably the most care throughout fabrication. Since I purchased the wafer with a pleasant prime quality oxide on it already that was capped off and saved clear by the thick polysilicon layer, I used to be in a position to get rid of all of the aggressive cleansing chemical compounds (sulfuric acid, and many others) from the method and nonetheless make nice transistors. Minimal course of chemical compounds and instruments are listed beneath.

Chemical substances utilized in residence poly-gate course of:
-Phosphoric acid
-Developer (2% KOH)
-N sort dopant (filmtronics P509)
-HF (1%) or CF4/CHF3 RIE
-HNO3 for poly etch or SF6 RIE
Gear utilized in residence poly-gate course of:
-Tube furnace
-Lithography apparatus
-Vacuum chamber to deposit metallic

Z2 “gate first” course of (just like normal self-aligned course of however and not using a area oxide):

I snapped one of many take a look at chips in half (useful Z2 however with unhealthy layer alignment and skinny metallic, about 300nm) and put it in my SEM for a cross part:

See Also

Discover the mud particle within the purple circle beneath, use that to get oriented within the coming cross part views.


Xsection (1)

NMOS cross section
NMOS cross part

As a result of I purchased the wafer already with gate oxide and polysilicon on it, I can’t develop a area oxide. These thick oxide layers are sometimes used to masks dopants and require a protracted excessive temperature step which might oxidize all of my poly and there could be none remaining. So, my modified course of makes use of a further masking step (the “gate” masks is usually not present in a self-aligned course of) that enables me to make use of the polysilicon itself as a dopant masks and hard-baked photoresist as the sphere dielectric. This various processing leads to the stepped construction you possibly can see within the orange area on the NMOS cross part above. This course of subtlety is talked about right here, read this twitter thread.

Gate length measurement
Gate size measurement

This course of isn’t perfect and I need to make some adjustments so it’s CMOS appropriate nevertheless it simplifies fabrication and makes it attainable with a minimal set of instruments. The 1µm dielectric layer (orange) would ideally be CVD SiO2 (it’s attainable to construct a TEOS oxide reactor at residence) however I used a photoresist as a substitute. Most photoresists may be baked round 250°C to type a tough everlasting dielectric layer that’s a straightforward various to CVD or PECVD oxide. A spin-on-glass/sol-gel is also used right here. SiO2 etching is completed with a buffered HF solution made from rust stain remover or RIE.

Enormous composite stitched die picture:


Thanks for following my work and be at liberty to contact me along with your ideas!

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