Seven Initiatives Innovating Round RISC-V

In One Year On. Thank You! I discussed that I had a couple of modifications deliberate to sharpen the main focus of The Chip Letter. Considered one of these modifications is to ‘Chip Letter Hyperlinks’ posts, which have, each couple of weeks, shared a variety of hyperlinks of curiosity. These posts have typically been enjoyable, however generally I’ve felt that the subjects lined might have appeared a bit … effectively, perhaps random?

So in future these ‘hyperlinks’ posts can have a typical theme. One thing that attracts every of the hyperlinks collectively. It is likely to be an organization, an structure, a programming language or simply an method to doing computing.

The ‘Chip Letter Hyperlink’s identify shall be retired however, I’ll attempt to preserve the die pictures which have began every put up, this time an AMD Radeon Fiji GPU, from Fritzchens Fritz, which is probably my favorite die shot to this point!

So on with at this time’s put up, which is about …

One may argue that an important take a look at of the success of RISC-V is just not whether or not the structure grabs market share from current architectures, however moderately whether or not it helps to spurs innovation.

This isn’t essentially round processor design. RISC-V is in lots of senses an ‘old-school’ RISC ISA with some refinements, so it could not drive future improvements in CPU design. Fairly, it is about innovation across the processor design itself, or about enabling initiatives that may in any other case have been harder or costly.

So I believed it might be attention-grabbing to take a look at a couple of RISC-V initiatives that might declare to be innovating across the RISC-V structure.

They’re a mixture of the extremely industrial and the extraordinarily enjoyable. They vary from startups with tens of thousands and thousands of {dollars} of funding, to pastime initiatives to construct ‘digital cores’ that run in on-line video games. From initiatives that goal to be on the slicing fringe of AI to these with a ‘retro’ flavour.

What all of them have in widespread is that designers will all have had a replica of the RISC-V ISA specification open on their desktop for prolonged durations. One may argue, in some circumstances, that if RISC-V did not exist then perhaps they’d have developed their very own ISA. It’s sure, although, that in every case that the existence of RISC-V saved the designers effort and it’s use has made the venture extra accessible to others.

Let’s begin with the extra formidable and critical, after which transfer on to the extra enjoyable initiatives.

P.S. Do please share when you have your personal favorite venture that’s innovating round RISC-V. Feedback can solely be accessed by paying subscribers however everybody can simply reply to this e-mail if you happen to’d wish to share a much less well-known venture. It could be nice to do a sequel!

Esperanto sits on the intersection of two teams of startups: RISC-V (with SiFive, Tenstorrent, Ventana and many others) and AI accelerators (with Cerebras, GraphCore and many others).

It has a pedigree that’s second to none. Dave Ditzel, its founder and govt chairman was co-author, with David Patterson, of the unique Berkeley RISC paper. He might have had an prolonged interval within the RISC wilderness engaged on x86 designs at Intel and Transmeta, however he’s now returned to his Berkeley RISC roots.

The corporate was based in 2014 and has, to this point, raised round $65m.

So what makes Esperanto progressive?

Here’s a slide that contrasts their method with different machine studying accelerators.

It’s utilizing heaps and plenty of RISC-V cores. To be particular, over a thousand of its ‘Minion’ cores, every with a vector/tensor unit, on a single die, organized into teams of ‘Minion Shires’. Right here they’re laid out on the Esperanto’s ET-SoC-1 Chip.

The ‘Minion’ cores themselves are constructed for low voltage operation and have a low gate depend – one thing that’s most likely enabled by the simplicity of the RISC-V ISA.

For a fuller clarification, right here is Dave Ditzel speaking about ET-SoC-1 at Stanford in 2022 and here’s a detailed presentation from Sizzling Chips 33.

In 2022 Esperanto claimed that:

The Esperanto ET-SoC-1 is the very best efficiency industrial RISC-V chip introduced to this point.

›  It has probably the most 64-bit RISC-V cores on a single chip.

›  It has probably the most RISC-V combination directions per second on a single chip.

›  It has the very best variety of TOPS on a chip pushed by RISC-V cores.

›  Esperanto’s low-voltage expertise offers differentiated RISC-V processors with the most effective efficiency per watt.

I’m greater than a bit sceptical about whether or not these new accelerators will change into mainstream (outdoors of Google’s TPU). You can argue that the Esperanto chip is simply one other design in a protracted collection which have tried to cram a lot of easy CPU cores onto a single die.

What strikes me, although, about Esperanto is how they’ve achieved this with so little funding. $65m {dollars} actually doesn’t sound like a lot in any respect for a venture like this that has constructed actual silicon on TSMC 7nm and which has been operating since 2014. I’m certain a part of the explanation for that is their potential to leverage RISC-V.

The subsequent venture goes again to the times of constructing computer systems from discrete parts. It’s a venture from Robert Baruch which Robert describes as:

The LMARV-1 (Study Me A Risc-V, model 1) is a RISC-V processor constructed out of MSI and LSI chips. You may level to items of the processor and see the info movement. It ought to be a pleasant manner of demonstrating how RISC-V works and the way easy it’s to implement.

There’s an accompanying collection of YouTube movies that debate the design (which is a reboot of an earlier model) intimately.

The venture is archived now and never underneath energetic improvement.

I assume you may argue that the venture is a regression moderately than innovation?

What’s progressive, although, is how Robert has been in a position construct such a easy design utilizing discrete parts for what’s a mainstream structure. He’s additionally, in fact, been in a position to share his work on the venture overtly.

The code for LMARV-1 is out there here.

After the break, RISC-V customized extensions in a really low cost microcontroller, a brand new type of arithmetic carried out in a core in India, the smallest RISC-V processor and RISC-V in Minecraft!

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not Tencent RISC-V!

Does being extraordinarily low cost, depend as progressive? Being low cost definitely permits innovation elsewhere.

A number of months in the past EEVBlog had a video on a ‘ten cent’ (sure that’s actually 10c) RISC-V microcontroller from a Chinese language firm known as WCH.

I feel it’s truthful to say that EEVBlog’s David Jones gave the CH32V003 a evaluate that was fairly optimistic.

“It appears to be like nearly as good as any mainstream processor. Hats off”

There are definitely cheaper microcontrollers, however few if any with this degree of processing energy.

So what powers this little Microcontroller? The QingKe (the web tells me that this implies ‘very quickly’ however maybe native audio system may verify or right me on this) V2 RISC-V processor, which is designed by WCH in-house, and which right here runs at 48MHz.

QingKe V2 collection microprocessor is a 32-bit general-purpose MCU microprocessor based mostly on the usual RISC-V instruction set RV32I subset RV32E, with solely 16 general-purpose registers, half of RV32I, and a extra streamlined construction for deep embedded eventualities. V2 collection helps customary RV32EC instruction extensions, along with customized XW extensions, {Hardware} Prologue/Epilogue (HPE), Vector Desk Free (VTF), a extra streamlined single-wire serial debug interface (SDI), and help for “WFE” directions. (Source)

It’s attention-grabbing {that a} core as low cost as this could have customized extensions – known as XW – one thing that would not be attainable with a licensed Arm core. Sadly, the one data I may discover on XW (from the QingKe V2 guide) was:

XW: 16-bit compression instruction for self-extending byte and half-word operations

Which sounds helpful, if not world altering.

Lastly, to indicate how engaged WCH are with the RISC-V world, right here is technical director Patrick Yang, with RISC-V co-funder Yunsup Lee.

We’re now going to return to AI and the subject of ‘posits’. Initially, what’s or are posits? It’s all about AI and numbers. IEEE Spectrum explains:

Coaching the massive neural networks behind many fashionable AI instruments requires actual computational would possibly … Engineers assume they’ve found out a method to ease the burden through the use of a special manner of representing numbers.

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Posits have been developed by John L. Gustafson and Isaac Yonemoto. In response to their paper:

A brand new information sort known as a posit is designed as a direct drop-in alternative for IEEE Commonplace 754 floating-point numbers (floats). Not like earlier types of common quantity (unum) arithmetic, posits don’t require interval arithmetic or variable dimension operands; like floats, they spherical if a solution is inexact. Nonetheless, they supply compelling benefits over floats, together with bigger dynamic vary, larger accuracy, higher closure, bitwise equivalent outcomes throughout methods, less complicated {hardware}, and less complicated exception dealing with.

Posits are literally the newest model of Gustafson’s Unum (Common Quantity) format. They usually appears to have generated plenty of curiosity.

Different groups are engaged on their very own {hardware} implementations to advance posit utilization. “It’s doing precisely what I hoped it might do; it’s getting adopted like loopy,” Gustafson says. “The posit quantity format caught hearth, and there are dozens of teams, each firms and universities, which can be utilizing it.”

So with its extensibility RISC-V would appear like a super base to make use of to take a look at the sensible points round implementation of posits. Enter PERI, a core that makes use of the SHAKTI RISC-V venture, from the Indian Institute of Expertise, as a base.

The article offers insights on how the Single-Precision Floating Level (“F”) extension of RISC-V could be leveraged to help posit arithmetic. We additionally current the implementation particulars of a parameterized and feature-complete posit Floating Level Unit (FPU).

The posit FPU has been built-in with the RISC-V compliant SHAKTI C-class core as an execution unit.

The paper then goes on to contemplate how posits examine with IEEE-754 floating level and to contemplate easy methods to combine with different RISC-V cores:

The article additional highlights the precise variations between posit and IEEE-754 in view of RISC-V and thereby concludes that posit simplifies designing of floating-point arithmetic considerably.

We additionally current an alternate methodology of exploiting the customized area of RISC-V ISA to combine the posit FPU as an accelerator with any RISC-V core supporting a RoCC like interface.

Word that this isn’t the primary time that RISC-V has been used as the bottom for work on posits – the Clarinet venture was first – however I feel it’s first in integrating with a mainstream core like SHAKTI.

An awesome instance of a gaggle making an attempt one thing out on an actual core, that may haven’t been attainable utilizing mainstream industrial architectures.

How small can a 32-bit core be? For the reply we will flip to SERV. In response to the venture’s README.

SERV is an award-winning bit-serial RISC-V core

Actually, the award-winning SERV is the world’s smallest RISC-V CPU. It is the right companion everytime you want a little bit of computation and silicon actual property is at a premium.

Other than being the world’s smallest RISC-V CPU, SERV additionally goals at being the most effective documented RISC-V CPU. For this there’s an official SERV user manual with block diagrams which can be right to the gate-level, cycle-accurate timing diagrams and an in-depth description of how issues work.

For an introduction, see this presentation ‘32-bit is the brand new 8-bit’ from developer Olof Kindgren.

To reply our unique ‘how small’ query, it’s attainable to suit 8 RISC-V cores right into a single low cost FPGA chip!

We’re going to finish with a few video games the place customers have constructed RISC-V processors inside the sport itself.

The video demonstrations actually communicate for themselves. First, in Minecraft:

Then in Terraria:

Don’t strive to do that at dwelling for x86!