Ternary ALU
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Working ternary ALU
02/12/2019
CMOS Implementation and Evaluation of Ternary Arithmetic Logic Unit
Louis Duret-Robert, Graduate Pupil in Electrical and Pc Engineering at Gerogia Institue of Know-how
Summary – Ternary logic is a substitute for binary logic utilized in each trendy processor. As a base-3 numerical system can symbolize numbers utilizing fewer digits than in base-2, ternary logic circuits are theorized to be extra compact than equal binary circuits. This enhance in density might result in a acquire in efficiency measured in transistor price, maximal frequency and vitality consumption. On this venture, the small print of balanced ternary algebra are reviewed and a ternary Arithmetic Logic Unit (ALU) is designed and constructed utilizing CMOS chips to show the feasibility of huge ternary CMOS circuits. Lastly, a theoretical evaluation of the advantages of balanced ternary logic is introduced. The conservative conclusion of this evaluation is that balanced ternary might be cheaper and sooner than equal fundamental binary logic, nonetheless, binary logic has many years of optimization methods making it method cheaper and sooner.
Key phrases – ternary computing, processor structure, ALU design, many-valued logic
Introduction
Motivation
Each trendy pc makes use of binary logic, 1s and 0s, for computations. Theoretically, any numerical base can be utilized for computation ^{[1]}. The numerical base (or radix) defines what number of digits can be essential to symbolize a sure quantity, that is the radix financial system and is written as $$E(b,N)$$ for base $$b$$ and quantity $$N$$ and calculated with the next components.
££ E(b,N) = b lfloor 1+log_b N rfloor££
The bottom common radix financial system is reached for base $$e approx 2.72$$ ^{[2]}. The closest integer base is $$3$$, not $$2$$ ; ternary not binary, and leads on common to the smallest radix financial system.
Due to this fact, a pc utilizing ternary logic may very well be extra environment friendly by requiring much less digits and fewer circuitry for a equally highly effective processor. Essentially the most well-known ternary pc was the Setun made by the soviets within the Nineteen Seventies and was extra environment friendly ^{[3]}. Nevertheless, binary processors are simpler to develop and binary received. As Moore’s regulation slows down, it is perhaps time to deliver ternary computing again to realize efficiency.
Switching to ternary logic requires redefining a complete new algebra, and a extra complicated one because the variety of doable states and thus gates is bigger.
Ternary algebra
Ternary values
Because the binary set of values is written $$mathbb{B}={0,1}$$, the image $$mathbb{T}$$ can be used for the set of ternary values. There exist a number of ternary units of values and thus a number of algebras : maybe the obvious is unbalanced ternary with $$mathbb{T}={0,1,2}$$ ; unknown-state ternary with $$mathbb{T}={F,?,T}$$ just like an epistemological set of reality values and an extension of the Boolean True-False interpretation of binary logic ; and balanced ternary $$mathbb{T}={-,0,+}$$ ^{[4]}.
Balanced ternary logic can be used on this report. It permits operations on adverse and optimistic numbers by default with-out having to make use of the ternary equal of two’s complement. Consequently, if we solely use the optimistic numbers, the vary of doable values is halved. This selection advantages unsigned operations over signed operations.
In follow on {an electrical} pc, balanced ternary could be represented by optimistic, adverse and nil voltage. Unique ternary computer systems might use micro-fluid route or gentle polarization. Using ternary logic for quantum computation won’t be mentioned on this report.
Analogous to the binary 8-bit byte and 4-bit nibble, a 3-trit phrase might be referred to as a tribble and a 9-trit phrase a tryte. The phrase tryte has additionally been used for a smaller 6-trit phrase, however doesn’t observe powers of three. A byte is 2 nibbles. A tryte is three tribbles.
One-input gates
In binary, a gate with one enter and one output might be represented as a two by one matrix.
Could be written with the matrix
££
start{bmatrix}
1
0
finish{bmatrix}
££
Due to this fact there are $$2^2=4$$ doable one-input one-output matrices in binary :
Matrix | Schematic | Description | Title |
---|---|---|---|
$$ start{bmatrix} 0 0 finish{bmatrix} $$ |
Clear | CLR | |
$$ start{bmatrix} 1 1 finish{bmatrix} $$ |
Mark | MRK | |
$$ start{bmatrix} 0 1 finish{bmatrix} $$ |
Id, buffer or move | BUF | |
$$ start{bmatrix} 1 0 finish{bmatrix} $$ |
Inverter | NOT |
Solely the final two are helpful.
In ternary logic, one-input one-output gates might be represented with a 3 by one matrix. There are $$3^3=27$$ doable such gates. Listed below are the significant ones ^{[5]}.
Most of them are solely helpful in uncommon conditions when constructing a processor. We are able to additionally be aware that ISZ is similar gate as NNOT. Those to recollect are the buffer and the three inverter gates.
Two-inputs gates
As with one-input gates, two-inputs gates will also be represented with a matrix. For a easy binary OR gate :
Could be represented with the matrix
££
start{bmatrix}
0 & 1
1 & 1
finish{bmatrix}
££
There are $$2^{2^2}=16$$ doable binary two-inputs gates. The three helpful ones with their inverted variations are :
In ternary logic, two-inputs gates are represented with a 3 by three matrix. Thus there are $$3^{3^3}=19683$$ doable such gates. Solely six helpful gates and their inverted variations can be de-scribed, nonetheless another gates might be helpful corresponding to some asymmetrical gates (as in switching the inputs produces differ-ent outcomes and the matrix is asymmetrical).
AND and OR ternary gates are generally referred to as MIN and MAX for apparent causes. The MUL gate can be generally referred to as XOR.
The gate symbols used listed here are just like the US binary gate symbols with modifications for the extra complicated operations. As well as, as with the US symbols, a dot on the output signifies an inverted output. The small triangle signifies that it is a ternary gate, to distinguish between equal binary and ternary gates. The symbols are primarily based on the binary AND and OR gates : if we solely take a look at the two×2 submatrix for zero and optimistic inputs of the ternary gates, some appear to be binary AND and different like binary OR, so that is the bottom used for his or her symbols, then alterations are added.
Formulae
Some gates are straightforward to implement with few transistors and resistors, whereas others require combining different less complicated gates. This will increase the fee but additionally the transmission time of the sign by way of the gate and thus the size of the transient earlier than reaching the static section with the right output of the circuit. This is usually a bottleneck for the frequency of a logic circuit corresponding to a processor. Due to this fact, discovering the perfect implementation of a gate is crucial.
To seek out the formulation of logic gates from easy ones, I Python script is used to check each doable mixtures of fundamental logic gates with easy operation prototypes. As an illustration, each mixture with the sample $$A bigstar B$$ with $$bigstar$$ a two-inputs gate. The script searches all of the mixtures for the best options with the smallest transistor and resistor price.
As can be defined when wanting on the CMOS implementation of these gates, the straightforward one-input gates are BUF, NOT, NNOT, PNOT in addition to CLU and CLD if we permit using diodes. The easy two-inputs gates are NAND, NOR, NCONS and NANY.
As with binary algebra, many formulae assist implementing the extra complicated gates. A few of the formulae are solely helpful be-cause they correspond to the CMOS implementations coated later.
$$overline{overline{A}}=A$$ | $$|A| = overline { overline{A} occasions A}$$ |
$$A^{=-}=examine{A}$$ | $$left lceil{A}proper rceil = A + (0)$$ |
$$A^{=+}=overline{hat{A}}$$ | $$left lfloor{A}proper rfloor = A occasions (0)$$ |
$$A$$^{╯╯}$$=A$$^{╮} | $$overline{A occasions B}=overline{A} + overline{B}$$ |
$$A$$^{╮╮}$$=A$$^{╯} | $$overline{A + B}=overline{A} occasions overline{B}$$ |
$$A^+ = A⊞(+)$$ | $$overline{A⊠B}=overline{A}⊠overline{B}$$ |
$$A^- = A⊞(-)$$ | $$overline{A⊞B}=overline{A}⊞overline{B}$$ |
$$A$$^{╯}$$ = A oplus (+)$$ | $$A otimes B=overline{A} otimes overline{B}$$ |
$$A$$^{╮}$$ = A oplus (-)$$ | $$overline{A oplus B}=overline{A} oplus overline{B}$$ |
$$overline{A otimes B}=overline{A} otimes B=A otimes overline{B}$$ |
$$A$$^{╯╮} $$=A$$^{╮╯}$$=A$$^{╮╮╮}$$=A$$^{╯╯╯}$$=A$$ |
$$A otimes B = (A + overline{B}) occasions (overline{A} + B) $$ |
$$A otimes B = overline{ overline{A occasions B} occasions A + B } $$ |
$$overline{A otimes B} = overline{ overline{A + B} + A occasions B } $$ |
$$A oplus B = left( A⊞B ⊞ overline {A⊠B} proper) ⊞ overline {A⊠B}$$ |
$$A oplus B = overline{ overline{ A⊞B ⊞ overline {A⊠B} } ⊞ A⊠B }$$ |
$$(A occasions B) ⊠ (A+B) = A⊠B$$ |
Primary CMOS implementations
CMOS chip choice
With a purpose to assess the feasibility of ternary processors, implementations of the essential ternary logic gates can be first be described. Present processors use Complementary Metallic Oxide Semiconductor (CMOS) logic with each PMOS and MNOS. With out entry to costly micro-fabrication, CMOS circuits can be constructed utilizing the CD4007 chip. This chip incorporates three CMOS pairs however just one is usable as they don’t seem to be unbiased. This chip is available in a DIP14 package deal, very helpful for assessments on breadboard and for customized PCB with DIP sockets to vary the chip if it breaks down.
This chip works with voltages as much as $$15V$$ so an adjustable dual-rail energy provide is used to check totally different configurations.
Elementary gates
The ternary inverter really is available in three variations, the impartial NOT and the optimistic and negatively biased NNOT and PNOT, however they do not require extra circuitry : only a single CMOS pair. The opposite fundamental gates have two inputs, thus two CMOS pairs. For the two-input gates, the 2 corresponding transistors of the 2 CMOS pairs can both be setup in parallel or in collection. Two configurations for the NMOS and the PMOS, so 4 configurations in whole for the 2 pairs. These are the 4 fundamental gates : NAND, NOR, NCONS, NANY ^{[6]}^{[7]}.
Be aware that the non-inverted two-inputs gates requires an extra common inverter on the output of the less complicated inverted variations.
The CD4007 CMOS pair has a small adverse voltage bias so the facility provide is ready to $$-5V$$ $$+5.7V$$. Two $$1kΩ$$ resistors are used between the PMOS and NMOS to stabilize the output. Moreover, a voltage shifter utilizing a small $$2.2V$$ Zener diode and a $$100kΩ$$ pull-down resistor to floor are used to create a flat and impartial zero state. With out the voltage shifter, the impartial state akin to a 0 is on a slope, making it unstable when utilizing the output to drive one other gate, as might be seen on determine 2.
Multiplication gate
The extra complicated multiplication gate requires the mixture of the basic gates described above, following the components listed beforehand.
$$A otimes B = overline{ overline{A occasions B} occasions A + B } $$
This equal circuit makes use of $$7$$ CMOS pairs when implementing every gate individually. Some transistors might be factorized to scale back the price of this gate ; nonetheless, this requires transistor-level management of the circuit which isn’t doable utilizing the CD4007 chip. Due to this fact, this won’t be explored on this paper.
The inverted multiplication gate might be constructed utilizing the identical variety of transistors, which might be helpful in sure circuits.
Addition gate
The addition gate is a crucial part for ALU circuits so a working low-cost implementation is a serious problem. As with the multiplication gate, the sum gate might be carried out utilizing the basic gates.
$$A oplus B = left( A⊞B ⊞ overline {A⊠B} proper) ⊞ overline {A⊠B}$$
This equal circuit makes use of $$11$$ CMOS pairs. Nevertheless, the inverted model of the sum gate is cheaper because it makes use of one much less inverter, thus one much less CMOS pair. Once more, some transistors might be factorized to scale back the price of this gate.
Ternary ALU design
Primary design
The principle operation of the Arithmetic Logic Unit is the addition. This operation, as in any numerical base requires a carry system, a method to propagate the carry from the addition from one digit to the subsequent. For the sake of simplicity, a ripple-carry system can be used on this design and never a carry-lookahead. Meaning including the 2 trits of 1 digit of the phrases requires the carry of the earlier pair of digits, due to this fact we now have to attend for the earlier sum to be accomplished. Consequently, because the phrase size will increase, so does the time required for the operation to finish in a linear method. In a full processor, this reduces the utmost frequency, or requires complicated timing and scheduling.
As with binary, we begin by making a half-adder, which add two trits and outputs the sum in addition to the carry of this operation. The matrices of the sum and carry of two trits are given in determine 5. We acknowledge the sum of A and B to be the SUM gate and the carry is the CONS gate.
start{bmatrix}
+ & – & 0
– & 0 & +
0 & + & –
finish{bmatrix}
start{bmatrix}
– & 0 & 0
0 & 0 & 0
0 & 0 & +
finish{bmatrix}
$$
Thus, a ternary half-adder can simply be constructed.
Then two half-adders are mixed to create a full-adder so as to add two trits in addition to the earlier carry. The carries of the 2 additions additionally need to be mixed with an ANY gate.
That is the center of the ALU. The primary and final additions of the chain of digits are particular as they respectively don’t have a earlier carry and don’t need to output a carry. Due to this fact, the primary digit solely requires one half-adder, and the final one requires two SUM gates.
Some ALU additionally embody a flag sign for the overflow (when the operation leads to a quantity exterior the vary of the structure). It may be achieved by changing the circuitry of the final digit with a common full-adder. This after all will increase the fee.
Subtraction
As defined earlier, balanced ternary logic permits straightforward operations utilizing optimistic and adverse numbers. To negate a ternary quantity, the one course of is to inverter each trit. This, an ALU that does solely addition can do subtraction by negating one of many inputs.
A easy circuit to negate a ternary phrase makes use of multiplication gates. Every trit of the phrase is fed in a multiplication gate and a typical sign is used to regulate the signal of the output phrase.
Optimization
The variety of CMOS pairs used for the ALU circuit might be decreased. Solely the addition circuit can be thought of right here.
First, the basic gate of the ALU is the SUM gate. The SUM gate prices $$11$$ CMOS pairs. Then to construct a half-adder, a SUM gate and a CONS gate are wanted for a complete of $$14$$ CMOS pairs. Then the full-adder requires two half-adders and an ANY gate, $$31$$ CMOS pairs. The primary digit of the ALU is a single half adder (as a result of there is no such thing as a incoming carry trit), $$14$$ CMOS pairs, and the final digits is 2 SUM gates (no output carry trit, regardless that it’s typically the case that the final carry bit in a binary ALU is saved in a flag for branching directions and the flexibility to do calculations with a number of phrases), $$22$$ CMOS pairs ; the remaining are full-adders. For a n-trit ALU ($$n≥2$$), the full price of the ALU (not together with the signal controller required for subtraction) is $$31n-26$$ CMOS pairs. For a 3-trit ALU, that quantities to $$67$$ CMOS pairs.
We are able to spare one CONS gate per half-adder through the use of the NCONS gate within the SUM gate and including a NOT gate. That saves $$2$$ CMOS pairs per half-adder. The brand new whole price is $$27n-20$$ CMOS pairs, $$61$$ CMOS pairs for a 3-trit ALU.
One other financial system comes from the formulae listed beforehand. If we invert each inputs of a SUM gate, the output is unchanged.
$$A⊠B=overline{A}⊠overline{B}$$
$$A⊞B=overline{A}⊞overline{B}$$
$$A otimes B=overline{A} otimes overline{B}$$
$$A oplus B=overline{A} oplus overline{B}$$
The trick is to make use of inverted gates earlier than the enter, and since these inverted gates are normally cheaper, we will save transistors. That is less complicated to know with diagrams.
Right here is another half-adder. Two symbols are used and right here is why. The circle on the output nonetheless signifies that the output is inverted in comparison with the default gate (right here the half-adder). The spherical cup on the enter is meant to point an inverter must be current on the enter ; that’s, to get the behaviour of the default gate, we now have to invert this enter. Right here, the 2 symbols, taken with the labels, are the identical : to get the behaviour of the default half-adder, we will both invert each output or each inputs. It is a direct consequence of the formulae listed above.
Utilizing this N-half-adder, we will create a N-full-adder.
Once more, each N-half-adders on this diagram correspond to the identical inside circuitry described above. Nevertheless, on the underside one, we feed the unique A and B indicators, so we get the inverted sum and inverted carry of A and B. Whereas on the highest one, we feed within the inverted incoming carry and the inverted sum from the primary N-half-adder, so we get the un-inverted last sum and the uninverted carry. So, one carry is inverted and the opposite is just not. To mix the 2 carries, we now have to invert one and thus add a NOT gate. Then, to get the inverted whole carry, a NANY is used, which is dearer than the ANY gate.
Lastly, the total ALU might be constructed once more. As anticipated, the primary and final digits are additionally totally different.
With these modifications, the N-half-adder prices 10 CMOS pairs, the N-full-adder 24 CMOS pairs, the primary digit 11 CMOS pairs and the final digit $$21$$ CMOS pairs. The whole and last price after optimization is $$24n-16$$ CMOS pairs, 56 for the 3-trit ALU.
Beside an financial system of transistors, the optimizations additionally scale back the variety of CMOS pairs the sign has to propagate by way of, and thus will increase the utmost frequency of the processor. Calculating the crucial path that can be defined later, a n-trit ternary ALU has a propagation delay of $$9n-7$$ CMOS propagation delays.
Additional financial system may very well be doable on the transistor degree as an alternative of pairs of transistors utilizing the CD4007 chips as a reference.
Bodily construct of the ALU
Sourcing supplies
The CD4007 chips had been purchased on ic-online.com. The customized PCBs had been designed on EasyEDA and manufactured by JLCPCB. All different electrical parts had been purchased from numerous suppliers on Aliexpress and eBay.
Ternary 2-trit ALU
With a purpose to confirm the feasibility of ternary logic circuits utilizing CMOS pairs, a 2-trit ALU with subtraction skill has been constructed. It makes use of virtually all of the gates described above together with the SUM and MUL gates.
A extra in-depth description of the design and testing course of in addition to an indication of the circuit in motion might be discovered within the different articles on this web site.
Comparability with binary
Metrics
Efficiency of processors might be measured on energy consumption, maximal frequency and price. Solely the latter two can be in contrast right here.
Maximal frequency is decided by the longest path of the electrical sign within the circuit, the crucial path. The time the sign takes to propagate by way of the circuit can rely on a number of elements, however solely the propagation time of the CMOS transistors can be thought of. The comparability can be measured utilizing the variety of propagation delays of the crucial path of the circuit. One CMOS propagation delay will refer to 1 propagation delay of the CMOS pair (about 20ns for the CD4007 for instance). Easy gates corresponding to NOT, NAND, NOR, NCONS and NANY solely require a single CMOS propagation delay, however the extra complicated MUL, SUM and NSUM gates require respectively $$3$$, $$6$$ and $$5$$ CMOS propagation delays.
Price itself might be damaged down on a number of elements. Processor fabrication prices are elevated by the expertise used, space of the die, variety of fabrication steps, and so forth. Within the case of ternary circuits, the expertise is just not explored on this report as it could require intensive experimenting utilizing micro-fabrication. The variety of transistors have an effect on instantly the realm of semiconductor obligatory. The variety of fabrication steps relies upon partly on the expertise used, and the density of interconnections between transistors requiring kind of layers on prime of the semiconductor. For the sake of simplicity and to get a primary thought of a comparability, the fee can be modelled by the variety of CMOS pairs obligatory.
Binary ALU design
The ternary ALU described above can be in comparison with a binary ALU utilizing the same design, that may be a n-bit ALU with a ripple carry system.
Utilizing comparable CMOS structure, the binary inverter (NOT) prices a single CMOS pair, and the binary NAND and NOR two-inputs gates price two CMOS pairs every. All three of these gates require a single CMOS propagation delay
The equal of the SUM gate of the ternary ALU in binary is the XOR gate. If we had been to implement this gate as a mixture of less complicated gates (binary NAND and NOR) as we did for the ternary SUM gate, we will use the next components.
$$A oplus B = overline{ overline{A + B} occasions (A occasions B) } $$
This brings the price of this gate to $$8$$ CMOS pairs. Utilizing binary algebra formulae, we will deduce that the fee for the XNOR gate is similar. The propagation delay is of $$3$$ CMOS propagation delays.
The binary half-adder is constructed with a XOR gate for the sum and a AND gate for the carry. The AND gate contained in the COR gate can be utilized to spare some transistors. Two half-adders are used to construct the full-adder and an OR gate combines the 2 carries.
This full-adder prices $$19$$ CMOS pairs and has a propagation delay of $$6$$ and $$7$$ CMOS propagation delays for the sum and the carry respectively. The primary little bit of the ALU solely requires a single half-adder and the final one solely two XOR gates utilizing the same structure to the ternary ALU.
Nevertheless, some processors use a unique implementation of the XOR gate utilizing Cross Transistor Logic ^{[8]}, the place the transistors are usually not related to the facility provide or floor, however to different gate outputs. This different logic household permits substantial price reductions but additionally require extra testing because the output of a PTL gate is just not instantly related to the facility provide however has to have the ability to drive different gates within the circuit. This could require extra circuitry. There exist many various PTL-like applied sciences corresponding to Double-Cross Transistor Logic, Swing Restored Cross Transistor Logic and Complementary Cross Transistor Logic. They won’t be in contrast on this report. Nevertheless, a typical PTL CMOS XOR gate might be constructed utilizing solely $$6$$ transistors.
Thus, the price of this XOR gate is simply $$3$$ CMOS pairs, and the delay is $$2$$ CMOS propagation delays. As this XOR doesn’t comprise a AND gate, we now have so as to add it. Nevertheless, we will use cheaper and sooner NAND gates.
This full-adder prices $$12$$ CMOS pairs and has a propagation delay of $$4$$ CMOS propagation delays for each the sum and the carry.
Each implementations can be thought of within the comparability. With out PTL logic, a n-bit binary ALU (with out the subtraction circuit) prices $$19n-14$$ CMOS pairs and has a propagation delay of $$7n-6$$ CMOS propagation delays. With PTL logic, a n-bit binary ALU prices $$12n-13$$ CMOS pairs and has a propagation delay of $$4n-3$$ CMOS propagation delays.
Outcomes
Plotting the anticipated price and propagation delay for various variety of digits within the three totally different architectures as a perform of the utmost vary of values, we get the next outcomes.
As we will see, whereas the proposed ternary ALU is considerably cheaper and sooner than the same binary ALU for equal most vary of values, utilizing Cross Transistor Logic brings a substantial benefit to binary over balanced ternary.
Essential evaluation
This comparability hints that ternary logic is just not a worthwhile various to binary. Nevertheless, binary logic has many years of advance in analysis, together with PTL optimization. Utilizing comparable CMOS design, balanced ternary nonetheless presents a bonus over binary. Due to this fact, it may be anticipated that transistor-level design optimization utilized to ternary logic can rival present binary processors.
Many assumptions have been made on this evaluation. A extra thorough evaluation would require experimenting on the semiconductor degree and bear in mind energy consumption as nicely.
Furthermore, this venture solely explores balanced ternary ALU. Unbalanced ternary logic would possibly require much less complicated circuitry for some parts of the processor corresponding to look-ahead carry techniques ^{[9]}.
Conclusion
Balanced ternary logic might be computed on CMOS circuitry, as proven with the conclusion of the ternary ALU proposed on this report. It’s total cheaper and sooner than comparable fundamental binary logic, nonetheless, many years of analysis on transistor-level optimization permit binary to surpass the ternary logic introduced.
Extra experimenting with different logic households corresponding to Transistor Cross Logic must be carried out to attempt to match the efficiency of optimized binary circuits. Analysis on the conclusion of ternary circuits in built-in circuits is required to conclude extra precisely on the potential features of ternary logic and its makes use of. Unbalanced ternary logic must be explored and in comparison with balanced ternary logic.
References
[1] Stanley L. Hurst. 1984. A number of-Valued Logic – its Standing and its Future. IEEE Transactions on Computer systems. Vol. c-33, No. 12, December 1984.
[2] C.B. Tompkins, J.H. Wakelin, Engineering Analysis Associ-ates Inc. 1950. Excessive-speed computing units. McGraw-Hill Ebook Firm Inc.
[3] N. Brusentsov, J.R. Alvarez. 2006. Ternary Computer systems : The Setun and the Setun 70. Soviet and Russian Computing. July 2006.
[4] W. Alexander. 1964. The Ternary Pc. Electronics and Energy. Vol. 10, Difficulty 2, February 1964.
[5] Douglas W. Jones. 2012. Commonplace Ternary Logic. The Ter-nary Manifesto. www.cs.uiowa.edu/~jones/ternary.
[6] H.T. Mouftah. 1976. A Research on the Implementation of Three-Valued Logic. Proceedings of the sixth worldwide sym-posium on multiple-valued logic, Could 1976, 123-126.
[7] H.T. Mouftah. 1978. Ternary Logic Circuits with CMOS Built-in Circuits. US patent 4,107,549, Aug. 15, 1978.
[8] R.P. MeenaakshiSundari, R. Anita, M.Okay. Anandkumar. 2013. Implementation of Low Energy CMOS Full Adders Utilizing Cross Transistor Logic. IOSR Journal of VLSI and Sign Processing. Vol. 2, Difficulty 5 (Could. – Jun. 2013).
[9] Douglas W. Jones. 2012. Quick Ternary Addition. The Ternary Manifesto. www.cs.uiowa.edu/~jones/ternary.