The Imperfect Artwork of Semiconductor Manufacturing And Lithography
All manufacturing on this planet is constructed upon stacking a number of processes and programs with numerous tolerances and variation ranges to get a persistently helpful product. Nowhere is that this extra evident than in semiconductor manufacturing as a consequence of being the one most intricate manufacturing course of with the bottom tolerance for error on this planet. Regardless of these challenges, the semiconductor trade has stacked lots of of abstraction layers on prime of one another for the software program world to see a constant system. Because the layers are peeled again, an excessive quantity of variation reveals itself.
Every chip that comes out of a fab, even when it’s the identical design, consumes a special quantity of energy for any given stage of efficiency. Many chips may have defects that result in the ultimate chip being yield harvested with a number of disabled “cores” and IO. For instance, all Nvidia A100 and H100 GPUs ship with ~10% of the chip disabled. The reason being the manufacturing variations embedded inside the billions of transistors and interconnects on trendy high-performance semiconductors, created with 1000’s of various course of steps. Every particular person transistor will take a special quantity of voltage to modify. Every part of interconnect, through, and get in touch with may have totally different resistance.
Let’s take a look at EUV lithography, as this is among the applied sciences central to manufacturing superior semiconductors. Our readers in all probability don’t want a crash course on lithography, however should you do, see these posts. 1, 2, 3, 4, 5, 6. From the supply of EUV mild to the mirror system to the photomask to the alignment system to the wafer stage to the photoresist chemical composition to the coater and developer to metrology to the person wafers.
EUV is a course of fraught with complexity, uncertainty, and imperfection, but it really works. TSMC, Samsung, and SK Hynix are all in manufacturing of EUV at various volumes. Intel has additionally confidentially acknowledged that they’re manufacturing prepared for EUV lithography of their Intel 4 course of node. We don’t actually imagine them as a result of inner paperwork we obtained present Intel’s first high-volume product using EUV, Meteor Lake, has been delayed but once more, with “ready-to-ship” dates delayed till Week 52, 2023 at minimal. This implies that Intel is dealing with challenges in implementing a production-scale design into an EUV course of expertise.
The buildup of slight variations in particular person course of steps can add as much as a major deviation from the specified end result, finally resulting in the failure of the ultimate product. For instance, points with laser drilling or precision casting in plane engines might result in a turbine blade being unbalanced. This unbalanced turbine will trigger extra vibration, decreasing effectivity and ultimately resulting in the engine sporting out and failing earlier. Now take into account that plane engines are considerably less complicated than semiconductors in manufacturing precision, course of variation tolerance ranges, chemistry, physics, and variety of steps.
Most instruments in a modern fab can deposit, polish, or etch supplies inside the precision of a handful of atoms. Every subsequent instrument within the chain of 1000’s of instruments/course of steps will consistently have its course of parameters tweaked. These situations and tweaks are decided by using course of management. Course of management contains metrology/inspection instruments and the software program which controls it. Fabs spend greater than $20 billion yearly on course of management.
If an etch instrument has 4 chambers, course of management intelligence, and fab community routing will decide which of the 4 chambers to ship wafers to based mostly on availability and yield metrics in that course of step. They will even modify the chamber situations and monitor if upkeep is required. In actual fact, even trailing edge fabs will tweak tool settings for each individual wafer or lot to maintain the gathered tolerance vary for every characteristic to a minimal viable specification.
To emphasise this level, the excessive stage of variation and uncertainty is so pervasive that manufacturing fabs will check a photomask with a number of totally different EUV instruments. These manufacturing fabs could run that photomask on just one particular EUV instrument that produces the very best yield or most manageable defects. Word {that a} trendy TSMC 5nm design has ~81 masks, and a single fab will run dozens or lots of of designs a 12 months. Moreover, photomask to EUV instrument matching is retested repeatedly as masks have to be serviced or remade on a semi-regular foundation.
Equally, even when metrology/inspection instruments of the identical kind are created and shipped from the identical facility, they could solely be used on choose layers as a result of excessive stage of tool-to-tool variation when measuring options which might be only some atoms in measurement. In actual fact, in some instances, greater than 25% of the error price range (stacked variations) is consumed by the uncertainty of the metrology and inspection imaging instruments. The instruments designed to supply the info to assist modify the instruments and processes in flight are additionally so imperfect that it’s like making an attempt to fly at night time.
Fabs have to leap via many, many holes to even belief that their metrology gear is giving them an correct image of what’s truly occurring on the wafers they’re processing. Lots of the errors and defects stem from EUV instruments and processes. EUV has 1/14th of the photons hitting the wafer relative to DUV on the identical dosage. As such, this introduces a substantial variety of stochastic defects stemming from a extra random distribution of fewer photons. Stochastics in EUV lithography refers back to the random variations that may happen in a sample.
These stochastic defects are a multi-billion greenback downside for the wafer fabrication trade. Tens of billions of {dollars} are spent characterizing variation with metrology and inspection instruments. The info generated right here is then fed again into the modifying course of or instrument parameters on a wafer-by-wafer, design-by-design, or tool-by-tool perspective. No two wafers, instruments, or designs are alike, and there’s a great quantity of adjustment and optimization on every of those fronts in a fab community.
A gigafab will run 1000’s steps throughout ~250,000 in-flight wafers, with ~100,000 ending over a month and a brand new 100,000 beginning over a month. The logistical challenges of routing, optimization, and making selections can’t be understated.
Stochastics usually are not simply rising linearly, however they’re rising exponentially as a proportion of the vital dimensions that we’re printing.
Chris Mack
We had the prospect to speak with Chris Mack, aka the “Litho Guru,” about many of those difficulties that the trade faces and among the options which have been developed. For these of you who don’t know, Chris Mack famously wager a Lotus Elise that EUV wouldn’t be prepared by a particular date on the SPIE Lithography and Superior Patterning convention. One other shaggy dog story is that he made and wore a pink “Make EUV Nice Once more” hat at this convention as a joke.
The SPIE Lithography and Superior Patterning convention is that this week. We repeatedly attend it because it covers all the newest developments within the photoresist, photomask, metrology, inspection, and lithography. When you’re at SPIE Lithography and Patterning this week, tell us, and we will chat!
There are a handful of main courses of variations and defects. These can all improve wire resistance, the leakage of a gate, and even trigger shorts or different defects that render a chip unusable.
As talked about earlier, a TSMC 5nm course of has ~81 photomasks. That is 81 totally different cases of going via all the lithography course of. As well as, there might be 1000’s of different manufacturing steps in between.
Overlay or native edge placement error is the variation of placement of 1 characteristic from a deposition, lithography, etch cycle on prime of one other characteristic from a previous cycle. A +1nm misalignment on one layer and a -1nm misalignment on the following layer stacks as much as a 2nm distinction within the placement of a characteristic. These types of errors can stack up cumulatively over many steps and could be catastrophic.
One instance we’ve got mentioned here is self-aligned contacts at TSMC vs. Intel, which try to mitigate among the stacking of overlay errors by making the patterned options extra proof against placement errors.
One other main supply of variation is native vital dimension uniformity. Options subsequent to one another ought to ideally be uniform if we would like them to be, however in lots of instances, they aren’t. On this instance, let’s zoom out to the vias and contacts that join numerous metallic layers of chips.
When these stochastic variations get massive sufficient, they end in defects lacking or merged: contact poles, bridges, and breaks and contours and areas. And you probably have 100 billion contacts/vias on a chip and considered one of them goes lacking, your entire chip is lifeless (some redundancy might be in-built, in fact). The trade should have at about one in 100 billion defect charges for options which might be solely tens of nanometers in diameter.
Line edge roughness (LER) is a variation within the edges of options. LER could be outlined because the roughness or irregularities within the edges of patterned options, corresponding to strains or trenches, which might result in deviations from the specified vital dimensions.
LER can have a major impression on the efficiency and reliability of the ultimate product. For instance, within the case of transistor gates, variations in LER can have an effect on the transistor’s electrical properties, resulting in points corresponding to elevated leakage currents and diminished system efficiency.
LWR could be outlined because the roughness or irregularities within the width of options, corresponding to strains or trenches, which might result in deviations from the specified vital dimensions. Within the case of metallic interconnects, variations in LWR can have an effect on the resistance of the strains, resulting in points corresponding to elevated energy consumption or diminished system efficiency.
The photomask could be regarded as the stencil of a chip. A photomask is patterned with ebeam and positioned contained in the lithography instrument. The photomask can then take in or scatter the photons or permit them to go via to the wafer. That is what creates the sample on the wafer.
OPC goals to right distortion or deformation of patterned options that happen in the course of the lithography course of. By compensating for them, producers can obtain larger accuracy and consistency within the patterned options, resulting in improved efficiency and reliability of the ultimate product. Beneath is an early type of OPC with extra superior situations, together with utilizing curvilinear ILT masks in quantity at TSMC.
We additionally will share 5 public corporations that might have outsized advantages from the chaos of lithography and artwork course of management. None of them are ASML or KLAC if that’s what you had been guessing.