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The clear chip inside a classic Hewlett-Packard floppy drive

The clear chip inside a classic Hewlett-Packard floppy drive

2023-12-20 13:05:11

Whereas repairing an eight-inch HP floppy drive, we discovered that the issue was a damaged interface chip.
For the reason that chip was unhealthy, I decapped it and took images.
This chip may be very uncommon: as a substitute of a silicon substrate, the chip is shaped on
a base of sapphire, with silicon and metallic wiring on high.
In consequence, the chip is clear as you may see from the gold “X” seen via the die within the picture under.

The PHI die as seen through an inspection microscope. Click this image (or any other) for a larger version.

The PHI die as seen via an inspection microscope. Click on this picture (or another) for a bigger model.

The chip is a customized HP chip from 1977 that gives an interface between HP’s interface bus (HP-IB) and the
Z80 processor within the floppy drive controller.
HP designed this interface bus as a low-cost bus to attach check tools, computer systems, and peripherals.
The chip, named PHI (Processor-to-HP-IB Interface), was utilized in a number of HP merchandise.
It handles the bus protocol and buffered information between the
interface bus and a tool’s microprocessor.1
On this article, I will have a look inside this “silicon-on-sapphire” chip, look at its metal-gate CMOS
circuitry, and clarify the way it works.

Silicon-on-sapphire

Most built-in circuits are shaped on a silicon wafer.
Silicon-on-sapphire, then again, begins with a sapphire substrate.
A skinny layer of silicon is constructed up on the sapphire substrate to type the circuitry.
The silicon is N-type, and is transformed to P-type the place wanted by ion implantation.
A metallic wiring layer is created on high, forming the wiring in addition to the metal-gate transistors.
The diagram under reveals a cross-section of the circuitry.

Cross-section from HP Journal, April 1977.

The essential factor about silicon-on-sapphire is that silicon areas are separated from one another.
For the reason that sapphire substrate is an insulator, transistors are utterly remoted, not like an everyday
built-in circuit. This reduces the capacitance between transistors, bettering efficiency.
The insulation additionally prevents stray currents, defending towards latch-up and radiation.
Due to its resistance to radiation, silicon-on-sapphire discovered use in house purposes.

An HP MC2 die, illuminated from behind with fiber optics. From Hewlett-Packard Journal, April 1977.

Silicon-on-sapphire built-in circuits date again to analysis in 1963 at Autonetics,
an progressive however now-forgotten avionics
firm that produced steering computer systems for the Minuteman ICBMs, amongst different issues.
RCA developed silicon-on-sapphire built-in circuits within the Nineteen Sixties and the RCA 1802 processor was used
on the Galileo spacecraft.
HP used silicon-on-sapphire for a number of chips beginning in 1977, such because the MC2 Micro-CPU Chip.
HP additionally used SOS for the three-chip CPU within the HP 3000 Amigo (1978), however the system was a industrial failure.
The recognition of silicon-on-sapphire peaked within the early Eighties and
HP moved to bulk silicon built-in circuits for calculators such because the HP-41C.
Silicon-on-sapphire remains to be utilized in
numerous merchandise, resembling LEDs and RF purposes, however is now principally a distinct segment know-how.

Contained in the PHI chip

HP used an uncommon bundle for the PHI chip. The chip is mounted on a ceramic substrate, protected by a ceramic cap.
The bundle has 48 gold fingers that
press right into a socket. The chip is held into the socket by two metallic spring clips.

Package of the PHI chip, showing the underside. The package is flipped over when mounted in a socket.

Bundle of the PHI chip, displaying the underside. The bundle is flipped over when mounted in a socket.

Decapping the chip was easy, however extra dramatic than I anticipated.
The chip’s cap is connected with adhesive, which will be softened by heating.
Scorching air wasn’t adequate, so we used a sizzling plate.
Eric examined the adhesive by poking it with an X-Acto knife, inflicting the cap to all of a sudden fly off with a loud “pop”
and sending the blade flying via the air.
I used to be blissful to be carrying security glasses.

Decapping the chip with a hotplate and hot air.

Decapping the chip with a hotplate and sizzling air.

After decapping the chip, I created the high-resolution die picture under.
The metallic layer is clearly seen as white strains, whereas the silicon is grayish and the sapphire seems purple.
Across the fringe of the die, bond wires join the chip’s 48 exterior connections to the die.
Barely higher left of heart, a big common rectangular block of circuitry supplies 160 bits of storage: this
is 2 8-word FIFO buffers, passing 10-bit phrases between the interface bus and a linked microprocessor.
The thick metallic traces across the edges present +12 volts, +5 volts, and floor to the chip.

Die photo of the PHI chip, created by stitching together microscope photos. Click for a much larger image.

Die picture of the PHI chip, created by stitching collectively microscope images. Click on for a a lot bigger picture.

Logic gates

Circuitry on this chip has an uncommon look as a result of silicon-on-sapphire implementation in addition to the
use of metal-gate transistors, however essentially the circuits are normal CMOS.
The picture under reveals a block that implements an inverter and a NAND gate.
The sapphire substrate seems as darkish purple. On high of this, the thick grey strains are the silicon.
The white metallic on high connects the transistors. The metallic may type the gates of transistors when it
crosses silicon (indicated by letters).
Inconveniently, metallic that contacts silicon, metallic that crosses over silicon, and metallic that kinds a transistor
all seem very comparable on this chip.
This makes it harder to find out the wiring.

This diagram shows an inverter and a NAND gate on the die.

This diagram reveals an inverter and a NAND gate on the die.

The schematic under reveals how the gates are carried out, matching the picture above.
The metallic strains on the high and backside present the facility and floor rails respectively.
The inverter is shaped from NMOS transistor A and PMOS transistor B; the output goes to transistors D and F.
The NAND gate is shaped by NMOS transistors E and F together with PMOS transistors C and C.
The elements of the NAND gate are joined on the sq. of metallic, after which the output leaves via
silicon on the precise.
Observe that alerts can solely cross when one sign is within the silicon layer and one is within the metallic layer.
With solely two wiring layers, alerts within the PHI chip should usually meander to keep away from crossings, losing quite a bit
of house.
(This wiring is far more constrained than typical chips of the Seventies that additionally had a polysilicon layer, offering
three wiring layers in complete.)

This schematic shows how the inverter and a NAND gate are implemented.

This schematic reveals how the inverter and a NAND gate are carried out.

The FIFOs

The PHI chip has two first-in-first-out buffers (FIFOs) that occupy a considerable a part of the die.
Every FIFO holds 8 phrases of 10 bits, with one FIFO for information being learn from the bus and the opposite for information
written to the bus.
These buffers assist match the bus velocity to the microprocessor velocity, guaranteeing that information transmission is
as quick as doable.

Every little bit of the FIFO is basically a static RAM cell, as proven under.
Inverters A and B type a loop to carry a bit. Cross transistor C supplies suggestions so the inverter loop stays
secure.
To write down a phrase, 10 bits are fed via vertical bit-in strains. A horizontal phrase write sign is activated
to pick out the phrase to replace. This disables transistor C and activates transistor D, permitting the brand new bit to
move into the inverter loop.
To learn a phrase, a horizontal phrase learn line is activated, turning on cross transistor F.
This permits the bit within the cell to move onto the vertical bit-out line, buffered by inverter E.
The 2 FIFOs have separate strains to allow them to be learn and written independently.

One cell of the FIFO.

One cell of the FIFO.

The diagram under reveals 9 FIFO cells as they seem on the die. The pink field signifies one cell, with
elements labeled to match the schematic.
Cells are mirrored vertically and horizontally to extend the format density.

Nine FIFO cells as they appear on the die.

9 FIFO cells as they seem on the die.

Management logic (not proven) to the left and proper of the FIFOs manages the FIFOs.
This logic generates the suitable learn and write alerts so information is
written to 1 finish of the FIFO and skim from the opposite finish.

The tackle decoder

One other fascinating circuit is the decoder that selects a specific register primarily based on the tackle strains.
The PHI chip has eight registers, chosen by three tackle strains. The decoder takes the tackle strains and
generates 16 management strains
(kind of), one to learn from every register, and one to write down to every register.

A die photo of the address decoder.

A die picture of the tackle decoder.

The decoder has an everyday matrix construction for environment friendly implementation.
Row strains are in pairs, with a line for every tackle bit enter and its complement.
Every column corresponds to 1 output, with the transistors organized so the column shall be activated when
given the suitable inputs.
On the high and backside are inverters. These latch the incoming tackle bits, generate the enhances, and
buffer the outputs.

See Also

Schematic of the decoder.

Schematic of the decoder.

The schematic above reveals how the decoder operates. (I’ve simplified it to 2 inputs and two outputs.)
On the high, the tackle line goes via a latch shaped from two inverters and a cross transistor.
The tackle line and its complement type two row strains; the opposite row strains are comparable.
Every column has a transistor on one row line and a diode on the opposite, choosing the tackle for that column.
As an illustration, supposed a0 is 1 and an is 0.
This matches the primary column because the transistor strains are low and the diode strains are excessive.
The PMOS transistors within the column will all activate, pulling the enter to the inverter excessive.
Nonetheless, if any of the inputs are “improper”, the corresponding transistor will flip off, blocking the +12 volts.
Furthermore, the output shall be pulled low via the corresponding diode.
Thus, every column shall be pulled excessive provided that all of the inputs match, and in any other case it will likely be pulled low.
Every column output controls one of many chip’s registers, permitting that register to be accessed.

The HP-IB bus and the PHI chip

The Hewlett-Packard Interface Bus (HP-IB) was designed within the early Seventies as
a low-cost bus for connecting various units together with instrument programs (resembling a digital voltmeter or frequency counter), storage, and computer systems.
This bus grew to become an IEEE normal in 1975, referred to as the IEEE-488 bus.2
The bus is 8-bits parallel, with handshaking between units so sluggish units can management the velocity.

In 1977, HP Developed a chip, referred to as PHI (Processor to HP-IB Interface) to implement the bus protocol and
present a microprocessor interface.
This chip not solely simplified development of a bus controller but additionally ensured that units carried out
the protocol constantly.
The block diagram under reveals the elements of the PHI chip. It isn’t an particularly complicated chip, however it
is not trivial both. I estimate that it has a number of thousand transistors.

Block diagram from HP Journal, July 1989.

The die picture under reveals a few of the practical blocks of the PHI chip.
The microprocessor linked to the highest pins, whereas the interface bus linked to the decrease pins.

The PHI die with some functional blocks labeled,

The PHI die with some practical blocks labeled,

Conclusions

Top of the PHI chip, with the 1AA6-6004 part number. I'm not sure what the oval stamp at the top is, maybe a turtle?

Prime of the PHI chip, with the 1AA6-6004 half quantity. I am undecided what the oval stamp on the high is, possibly a turtle?

The PHI chip is fascinating for example of a “know-how of the longer term” that did not fairly pan out.
HP put numerous effort into silicon-on-sapphire chips, anticipating that this may develop into an essential
know-how: dense, quick, and low energy.
Nonetheless, common silicon chips turned out to be the successful know-how and silicon-on-sapphire was relegated
to area of interest markets.

Evaluating HP’s silicon-on-sapphire chips to common silicon chips on the time reveals some benefits and drawbacks.
HP’s MC2 16-bit processor (1977) used
silicon-on-sapphire know-how and had 10,000 transistors and ran at 8 megahertz, utilizing 350 mW.
As compared, the Intel 8086 (1978) was additionally a 16-bit processor, however carried out on common silicon and utilizing NMOS as a substitute of CMOS. The 8086 had 29,000 transistors, ran at 5 megahertz (at first) and
used as much as 2.5 watts. The sizes of the chips had been nearly similar: 34 mm2 for the HP processor and
33 mm2 for the Intel processor.
This illustrates that CMOS makes use of a lot much less energy than NMOS, one of many causes that CMOS is now the dominant know-how.
For the opposite elements, silicon-on-sapphire had a little bit of a velocity benefit however wasn’t as dense.
Silicon-on-sapphire’s primary downside was its low yield and excessive value.
Crystal incompatibilities between silicon and sapphire made manufacturing tough; HP achieved a yield of 9%,
which means 91% of the dies failed.

The time interval of the PHI chip can be fascinating since interface buses had been transitioning from
easy buses to high-performance buses with complicated protocols.
Early buses could possibly be carried out with easy built-in circuits, however as protocols grew to become extra complicated,
customized interface chips grew to become obligatory.
(The MOS 6522 Versatile Interface Adapter chip (1977)
is one other instance, utilized in many dwelling computer systems of the Eighties.)
However these interfaces had been nonetheless easy sufficient that the interface chips did not require microcontrollers,
utilizing easy state machines as a substitute.

The HP logo on the die of the PHI chip.

The HP brand on the die of the PHI chip.

For extra,
comply with me on Twitter @kenshirriff or RSS for updates.
I am additionally on Mastodon often as @[email protected].
Because of CuriousMarc for offering the chip and to TubeTimeUS for assist with decapping.

Notes and references



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