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Transformer Inference Arithmetic | kipply’s weblog

Transformer Inference Arithmetic | kipply’s weblog

2023-05-13 03:17:21

This text presents detailed few-principles reasoning about giant language mannequin inference efficiency, with no experiments or tough math. The quantity of understanding that may be acquired this fashion is admittedly spectacular and sensible! A quite simple mannequin of latency for inference seems to be a great match for emprical outcomes. It is helped me make higher predictions and kind higher explanations about transformer inference.

This submit assumes some prior data about transformers, say at having understood most of The Illustrated Transformer however not having internalised all of it. Familiarity with this parameter counting submit which I developed together with this one may additionally be helpful.

Desk of Contents

  • kv cache explains the efficiency enchancment of caching self-attention vectors as part of inferencing, in addition to the potential tradeoffs and capability prices
  • capacity takes the storage price of kv cache and connects it to the storage price of mannequin weights and what capability means for efficiency.
  • model parallelism builds up an understanding particularly of tensor parallelism to obviously determine the price of communication
  • latency calculations pulls understanding from different ideas to create equations that function floorlines for inference velocity.
  • batch sizes discusses what impression batch measurement has on efficiency and what sizes could also be optimum.
  • flops counting steps by the transformer blocks and identifies which operations meaningfully contribute to flops velocity.
  • intermediate memory costs covers how the activations take further reminiscence and what that reminiscence bandwidth prices appears to be like like from some actual benchmarks.
  • comparing against real benchmarks compares what we are able to calculate to what Nvidia FasterTransformer benchmarks report and identifies the discrepancies.

kv cache

For sampling, transformer inference consists of processing a offered immediate/context (which might occur in parallel), after which sampling further tokens one after the other (that is the place the autoregressiveness surfaces). Within the sampling, the transformer performs self-attention, which requires the kv values for every merchandise at present within the sequence (whether or not it was immediate/context or a generated token). These vectors are offered a matrix generally known as the kv cache, aka previous cache (the open supply GPT-2 implementation referred to as it previous). The previous cache can be formed like [batch, 2, num_heads, seq_len, features].

The aim of that is to keep away from recalculations of these vectors each time we pattern a token. With the computed (ok, v ) values, we are able to save fairly a little bit of computation at the price of some storage. Per token, the variety of bytes we retailer is

The primary issue of two is to account for the 2 vectors, (ok) and (v). We retailer that per every layer, and every of these values is a ( n_text{heads}occasions d_text{head}) matrix. Then multiply by 2 once more for the variety of bytes (we’ll assume 16-bit codecs all through the submit).

The weights that we multiply by the token embeddings are (W_text{ok}, W_text{v} in mathbb{R}^{d_text{mannequin}occasions d_text{mannequin}}) after which every token embedding is (t_text{e}in mathbb{R}^{1times d_text{mannequin}}). So then the flops to compute (ok) and (v) for all our layers is

We multiply (t_text{e}) by (W_text{ok}), which takes (2 cdot {d_text{mannequin}}^2) flops. We’ve one other issue of two as we do this twice, as soon as every for (ok) and (v) after which repeat for (n_text{layers}).

What number of flops in a matmul?

The computation for a matrix-vector multiplication is (2mn) for (A in mathbb{R}^{mtimes n}, b in mathbb{R}^{n}). A matrix-matrix is (2mnp) for (A in mathbb{R}^{mtimes n}, B in mathbb{R}^{n occasions p}). The (mn) issue makes loads of sense, and the 2 comes from the truth that a matmuls are composed of multiply(1)-add(2) operations. Extra in these lecture notes.

This implies for a 52B parameter mannequin (taking Anthropic’s, the place (d_text{mannequin} = 8192) and (n_text{layers} = 64)). The flops are

Say we’ve got an A100 GPU, which does (312text{e}12) flops per second and (1.5text{e}12) bytes per second of reminiscence bandwidth. The next are numbers for simply the kv weights and computations.

Flops vs Reminiscence Boundedness

Flops vs reminiscence boundedness is one thing we cope with rather a lot for transformer inference, however also in deep learning optimisation in general. To do the computations we do, we have to load weights which prices memory bandwidth. We assume (accurately, this has been very properly optimised) that we are able to begin the computations whereas we load the weights. Flop certain would then imply that there’s time when nothing is being handed by reminiscence, and reminiscence certain would imply that no floperations are occuring. Nvidia makes use of the time period math bandwidth which I discover actually cute. Technically, this delineation exist per kernel however might be abstracted to exist for teams of operations.

Not one of the mannequin structure issues anymore — we get a definite ratio right here of 208 given this {hardware} specification. Which means that if we’ll compute kv for one token, it will take the identical period of time to compute for as much as 208 tokens! Something beneath, we’re reminiscence bandwidth certain. Above, flops certain. If we used the remainder of our weights to do a full forwards go (run the remainder of the transformer) on our context, it is also 208 (each the numerator and denominator get an element of 6 added). This might be reasoned completely in future sections. The intersection of the beneath diagram is at 208, although in actuality the reminiscence line does have a slight slope attributable to reminiscence price of intermediate calculations (mentioned within the final part).

For a 52B mannequin full forwards go, that is (12cdot 2 cdot n_text{layers} cdot {d_text{mannequin}}^2 / 1.5text{e}12 approx 69) milliseconds for as much as 208 tokens (in apply, we would use 4 GPUs in parallel so it might truly be ~17 milliseconds, extra in following sections). If we had 416 (double) tokens within the context, then it might take twice as lengthy, and 312 tokens would take 1.5 occasions as lengthy.

Calculating for a kv cache token is strictly 1/sixth of the compute of passing the token by the mannequin. Typically, these forwards passes (what we expertise in getting logits, embeddings and coaching) are very low cost due to the parallelism that’s potential versus sampling the place we’re pressured to learn by all of the weights for every token and do the autoregression.

This doesn’t suggest that 1/sixth of the time is saved! Let’s assume we’re flops certain. Then at every pattern step, we save (2 cdot 2 cdot n_text{tokens} cdot n_text{layers} cdot {d_text{mannequin}}^2 div 312text{e}12) flops whereas the decoding steps prices (2 cdot 12 cdot n_text{layers} cdot {d_text{mannequin}}^2 div 312text{e}12). Thus at every step we save 1/6 of the flops time multiplied by the variety of tokens in our sequence (large!) — which will increase as we pattern tokens. It’s the case that and not using a kv cache, sampling can be quadratic in time complexity as we enhance the variety of tokens.

This isn’t the entire story (given overheads and tradeoffs related to storing this cache). If we’re serving small batches we could also be reminiscence bandwidth certain quite than flops, wherein case we can’t even need to use the previous cache and can as an alternative fortunately do recomputations, spending the flops (we’ll already be paying the reminiscence price to do our sampling).


We’ve a stable concept of the 2 issues we retailer in our GPUs — kv cache and weights. GPU capability does come into play for transformer inferencing efficiency and we’ve got all of the understanding we have to consider that now!

Nvidia A100 GPUs (that are usually talking, the most effective GPUs we are able to get for inference) have a normal of 40GB of capability. There are ones with 80GB and better reminiscence bandwidth (2e12 as an alternative of 1.5e12) however they are not out there with any giant cloud providers but which suggests they are not actual to me!

Given the parameter rely, we are able to multiply by two to get bytes. So to calculate the scale of the weights for a 52B mannequin.

Oh no! This does not slot in one GPU! We might want no less than three GPUs simply to have all of the weights loaded in (will focus on how to try this sharding later). That leaves us (120-104 = 16GB) left for our kv cache. Is that sufficient? Again to our equation for kv cache reminiscence per token, once more with a 52B mannequin;

After which we would do (16/0.002 approx 8000) tokens can match into our kv cache with this GPU arrange, or that we may do as much as a batch measurement 4 the place every request has as much as 2048 tokens (and better sizes for much less tokens).

This sucks as a result of we wish to have the ability to do greater batch sizes, however are capability restricted! Greater batch sizes are extra environment friendly by way of how a lot GPU time it takes to course of the identical request. However, at batch sizes this low we’re certain to be reminiscence certain, and may forego the kv cache and simply pay the flops price as an alternative.

For 4 GPUs, we would get (56/0.002 approx 23000). We positively need to go for the 4 GPUs since we’ll need to have the ability to do greater batch sizes, and it is foolish to to divide powers of two over three GPUs. However it’s not simply batch measurement! If we’ve got excessive quantity, then we would have a number of cases of our fashions. We roughly need every occasion to have the ability to do as giant as a batch measurement as potential, as we pay the price of storing the weights anyway.

There’s some further area utilized by intermediate calculation steps, however they’re negligible.

mannequin parallelism

I am not going to construct up full understanding of mannequin parallelism and all of the implementation particulars, as a result of many have done so. However we are going to construct out the components of the understanding which can be helpful to determine to make efficiency selections and calculate communication prices!

The result of mannequin parallelism, is that the price of passing all of the weights by by reminiscence and the flops are all divided over the diploma (variety of accelerators we use).

We’ll assume tensor parallel (mannequin parallel) the place we are going to break up down the center of the mannequin. Every accelerator will execute as a lot as it may well with its shards of the weights and can talk every time synchronisation is required. A extra naive method is pipeline parallel, the place every GPU will maintain onto a fraction of the layers. This does efficiently even out the burden loading price, however has the plain foolish that each one however one GPU might be idling! In coaching you could possibly pipeline by it (as the primary batch strikes onto the subsequent GPU, begin on a brand new batch on the primary GPU) but it surely would not work out for a single pattern request (although you could possibly nonetheless do it for a number of requests). Pipeline additionally would not exhaust the reminiscence bandwidth, which is definitely okay in the event you’re flops certain anyway. The one place the place pipeline parallel does higher is communications. A pipeline parallel mannequin would talk (d_text{mannequin}) per accelerator, whereas a mannequin parallel does (Ncdot d_text{mannequin}) per layer the place (N) is the variety of accelerators.

Right here we introduce the final fixed for our A100 GPUs which is a communication bandwith of 300GB/s. The doc marks it as 600GB/s as a result of Nvidia is including up 300GB/s into every chip and 300GB/s out concurrently quite than utilizing a bidirectional quantity (which might be extra intuitive for our calculations).

On this diagram, we begin by following the yellow brick street the place we insert our token embeddings into the underside of the mannequin. The purple containers define how our weights can be break up throughout the accelerators, and we work with a particularly tiny mannequin so we are able to draw all the things to scale. A normal concept is that if we’ve got two matrices (X) and (Y) we are able to shard each of them and multiply the shards. This does not truly full the matmul of (Xcdot Y), and a simple method to inform (aside from our capacity to multiply matrices) is that if we concatenated the results of multiplying the shards, we get too large of a matrix. As an alternative, we might need to talk, compute a shard sum, talk that sum again out after which concatenate for the output of (X cdot Y).

For consideration the parallelism is intuitive from the truth that we’ve got a number of heads. We undergo a lot of the consideration layer with out communication as a result of our consideration heads are concatenated to multiply by (W_o). After we multiply by (v), we multiply the end result by our shard of (W_o) to get a shard of (o_s in mathbb{R}^{d_text{mannequin}occasions n_text{heads}/N}). Then every accelerator will talk its personal shard to all of the others, and all of the others will talk their shards again. That is ((N-1)d_text{mannequin}/N) of comms price. Every accelerator will do a good share of the addition to get the output projection, then do the identical communication they did final time and the person hosts will do the concatenation (roughly on the spot).

The MLP layer is by nature very comparable! Similar to we’ve got (W_o) to undertaking our multi-headed consideration outcomes again right down to a vector of size (d_text{mannequin}), we’ve got (W_1in mathbb{R}^{4times d_text{mannequin}}) and (W_2in mathbb{R}^{d_text{mannequin}occasions 4}) to make a dimension 4 occasions bigger after which undertaking it again down. The identical two communications are executed on the finish of the MLP.

Finally we do (4 cdot (N – 1)d_text{mannequin}/N) bytes of communication. The kv cache is break up throughout heads by GPU.

latency calculations

We have mentioned the capability pretty completely, mapped out comms within the mannequin parallelism part and mentioned normal compute steps. Now we’ll construct it into equations that estimate latency!

Our latency calculations are principally in regards to the flops vs reminiscence boundedness. If we’ve got a small variety of multiplies to do per parameter, then possibly we’ll be throttled by reminiscence bandwidth. Flops are elevated by each batch measurement and variety of parameters, whereas reminiscence is just elevated by variety of parameters.

For comms, it is not about boundedness, however quite about including a latency time period and a throughput time period (the 300GB/s). One thing difficult in regards to the latency facet of this determine is that it is not reported, so the most effective I can do is guess “roughly small”, which is roughly 8 microseconds per message despatched as discovered on this Citadel paper but it surely’s for V100 NVLink.

Due to the compute components, to calculate the latency of a single token decoding step we would have two formulation – one for reminiscence bandwidth certain (small batch) and one other for flops certain (giant batch). For big batch, we’ll drop the latency issue for communications.

Equations for a small batch (say 1, so we are able to drop the batch issue) can be; (the place (N) is the variety of accelerators and (P) is the variety of parameters and (b) is “byte” as a unit)

There may be (2 cdot P) as a result of we have to go all of the parameters by the reminiscence, and every parameter is 2 bytes. (A_text{bm}) is the accelerator reminiscence bandwidth, and this price is break up throughout accelerators. For comms, we’ve got ( 4 cdot n_text{layers} ) communications per layer, and the latency per every request. Comms will often come out to be comparatively small so for the compute certain case we can’t want to concentrate to it anyway. There’s additionally a throughput price in comms which additionally rounds away.

There’s one other sometimes-significant issue right here which is the learn time for the kv cache, which I will miss of the equation now because it is determined by variety of context tokens, which might even range inside a batch and complete variety of tokens we need to pattern. This is able to be calculated as reminiscence bandwidth time. One other lacking reminiscence bandwidth time is the learn of the unembeddings to calculate logits at every sampling step, which is ( in mathbb{R}^{d_text{mannequin}occasions n_text{vocab}}).

As beforehand talked about, the reminiscence doesn’t truly keep fixed, quite some further reminiscence is used per batch for intermediate activations. The explanation we do not issue this in is just because it is onerous to rely because it varies rather a lot by the software program stack, compiler optimisations, and many others.

For big batches (say 512), the place (B) is the batch measurement;

The place (A_f) is the flops of the accelerator and (A_c) is the comms bandwidth. We do (2cdot P) flops of operations, which might be intuited by the truth that we matmul by all of the parameters, and as talked about earlier, a matrix-vector multiplication is (2mn) given (A in mathbb{R}^{mtimes n}, b in mathbb{R}^{n}).

For comms, we see the 4 (I will spherical that (N-1) issue to (N)) communications every of a (d_{mannequin}) measurement vector per layer as defined within the mannequin parallelism part. We swapped out the latency calculation for a throughput one. Then it is all divided by the comms bandwidth.

Let’s play with a bigger mannequin, a Gopher sized 260B mannequin on 16 GPUs. For a small batch, it is 22 ms per token generated. The throughput price for the comms which we are able to calculate with the equation for big batch is roughly 35 microseconds, assuring us that it was secure to drop.

For a big batch of 512, for a complete of 53 ms per token generated (per batch, so within the 62ms 512 tokens are generated). The latency price on comms right here would’ve additionally been 3ms (latency shouldn’t be multiplied by batch because the message might be ready collectively) which is considerably vital to drop but it surely’s tremendous if we assuming parallel comms and compute.

The upper worth between the comms and compute is taken as we’re assuming that it’s parallel. Thus, we might need to keep away from having comms being better than compute (that is the mechanism that stops us from approaching latency zero as we insert extra chips, ultimately the comms will begin taking increasingly more time). It isn’t assured that each one methods will do that in parallel, and positively not completely in parallel.

These numbers are positively a lot decrease than what we are able to get with actual sand, because it assumes optimum {hardware} utilization, would not think about softmaxes, assumes zero comms latency and ignores many different smaller components. Nonetheless, all of the reasoning behind this math is helpful for interested by the place to go optimise efficiency what deltas incoming optimisations will trigger.

batch sizes

Batch measurement is a crucial issue of our efficiency, particularly in direction of understanding efficiency for particular usages.

Within the earlier part, we’ve got two calculations for when one thing reminiscence bandwidth certain versus flops certain. To determine which is at play we are able to evaluate these numbers;

We’re coping with the identical ratio we discovered within the kv cache part. The min batch measurement for reminiscence bandwidth certain is (A_text{bw}/A_f = 208). This can be a helpful ratio! If we’ve got the load to do it, we favor flops certain because it’s extra compute environment friendly. Although it is also the case that if we’re flops certain, making the batch measurement bigger does not imply something is getting quicker.

To calculate when the capability goes from principally kv cache to principally weights is trivial, and likewise is not a binary in the identical method (nothing particular occurs when your kv cache begins taking on extra reminiscence than your weights). Nothing particular actually occurs with comms both. In some unspecified time in the future in growing the batch measurement, the throughput begins dwarfing the latency so we dropped that issue. As noticed beforehand, the latency turns into insignificant a lot later (our 512 batch on 52B communication price was nonetheless 11% latency).

One thing oversimplified about comms is that it occurs at 4 totally different steps, which suggests we do not simply need our compute time to be longer than our comms time, we would like it to be the case at every step (if we are able to parallelise the compute and comms). For that, we’ve got a weirder ratio: flops per byte of comms. This is a pleasant chart of our computations, which may even be helpful within the part beneath.

(q, ok, v) (o) (w_1) (w_2)
flops (3B({d_text{mannequin}}^2)) (B({d_text{mannequin}}^2)) (4B({d_text{mannequin}}^2)) (4B({d_text{mannequin}}^2))
bytes of comms (B(d_text{mannequin})) (B(d_text{mannequin})) (B(d_text{mannequin})) (B(d_text{mannequin}))
flops/byte (3(d_text{mannequin})) (d_text{mannequin}) (4(d_text{mannequin})) (4(d_text{mannequin}))

(312text{e}12 div 300text{e}9 = 1040), which is our flops per byte of comms for our A100s. We would like the values within the final row to be bigger than our {hardware} flops per byte in order that we keep flops certain (assuming we aren’t reminiscence certain right here). For any mannequin with an embedding dimension over 1024 (per chip), we’re secure! For 512, it is a bit of awkward.

A low-load API could end in smaller batch sizes, resulting in affordable selections like dropping the kv cache. If an API had the load for big batches it might in all probability need to serve the bottom batch measurement that will get flop certain even when there’s capability left in order that it may optimise for per-request-latency. In say mass-inferencing jobs like AlphaCode we’d need to insert as many chips as we are able to after which do the most important batch we are able to do with that capability. I say “could” rather a lot right here however I truly assume these are absolute and all three sorts of circumstances.

flops counting


We do (2cdot P) flops of operations, which might be intuited by the truth that we matmul by all of the parameters.

That is appropriate reasoning, however we are able to break it down by strolling by all of the transformer steps and verify that we get (2P).

The next calculations are per token, per layer. I describe (W_q, W_k, W_v in mathbb{R}^{d_text{mannequin}occasions d_text{mannequin}}) the place it is extra correct to say we’ve got (W_q^i, W_k^i, W_v^i in mathbb{R}^{d_text{mannequin}occasions d_text{head}}), the place (i) goes as much as (n_text{heads}). However for the sake of calculating latency, I simplify (W_q, W_k, W_v) to incorporate all of the heads.

  • Computing qkv
    • Multiply (t_e in mathbb{R}^{1times d_text{mannequin}}) by (W_q, W_k, W_v in mathbb{R}^{d_text{mannequin}occasions d_text{mannequin}})
    • Flop rely: ({2 cdot 3 cdot d_text{mannequin}}^2)
  • Calculate z
    • That is (textual content{softmax}((qcdot ok)divsqrt{d_text{head}}) cdot v = z)
    • No matrices are multiplied, the variety of flops is a few issue of (d_text{mannequin}).
  • Multiply by the output projection matrix
    • Multiply (W_o in mathbb{R}^{d_text{mannequin}occasions d_text{mannequin}}), by (z in mathbb{R}^{d_text{mannequin}times1})
    • Flop rely: (2 cdot {d_text{mannequin}}^2)
  • Feed-forward
    • We’ve our MLP weights (W_1 in mathbb{R}^{4times d_text{mannequin}}, W_2 in mathbb{R}^{d_text{mannequin}occasions 4} ) for 2 linear transformations (there is a ReLU within the center, which small).
    • Flop rely: (2cdot 8 cdot {d_text{mannequin}}^2 )
  • Another issues
    • There are usually layernorm that occur after every consideration, the place the weights there are a vector of size (d_text{mannequin}).
    • There’s one other linear layer after which a softmax that sits on prime, which is our output (token) embedding or unembedding or de-embedding or embedding(^{-1}).
    • The unique transformer has a cosine absolute positional encoding scheme, which is an addition operation on the token embedding.

Including up all of the flops!

Subbing in our 8192 mannequin, we must always get about 100B flops;

103079215104 over two is about 51.5B. We’re a lil below (we get 51.5B as an alternative of 52B) however that is as a result of token (un)embeddings are practically a billion parameters. It will be affordable to do the latency calculations with (2cdot 12cdot n_text{layers} cdot {d_text{mannequin}}^2) as an alternative of (2cdot P), but it surely’s lower than a 2% distinction.

What in regards to the the calculation of (z) and all the opposite steps I did not rely? These are all vector-vector (and even vector-scalar) operations, so they’re constructed round an element of (d_text{mannequin}) quite than ({d_text{mannequin}}^2). Even when we had 100 of those operations per layer, it might come out to 100 million flops, which is 0.1% of the variety of flops we counted.

intermediate reminiscence prices

Data Movement Is All You Need (which is usually about optimising low stage information motion for transformers, and is not a very related learn) has a pleasant method of classifying operations. We’ve tensor contractions, that are the large matmuls we have principally cared about (together with the linear layers). Then there are statistical normalisations, the softmax and layernorm. Lastly, which this submit has fully ignored until now are element-wise operators, that are issues like biases, dropouts and activations.

So how will we calculate the latency of these matmuls, layernorms, and many others? The reported flops on our {hardware} is specificially for the multiply-add operations so it might not be proper to rely it in there even when we may rely the flops. Shock! It is solely to price reminiscence to do the softmax learn/writes as that is what the bandwidth to flops ratio favours. That is the latency issue that has been alluded to!

I will break character on the first-principles facet of this and focus on Desk A.1 from the Data Movement Is All You Need paper. Right here we see that the latency for softmax is definitely barely greater than the calculations for qkv (that are a 1/3 of the time). This can be a little regarding!

For a similar motive the softmax is reminiscence certain, so is the multiplication of qk, ReLU and dropout are additionally fairly costly.

GPU Kernel Fusion

See Also

GPUs execute operations in items of “kernels”. Kernel fusion implies that one thing that was often 2 kernels can grow to be one, and the first use is to reuse hundreds into reminiscence and scale back redundant hundreds and shops. For instance, a multiply-add is one kernel. If it have been two, then one would load+add+retailer and the second would load+multiply+retailer. We may save loads of journeys by doing load+add+multiply+retailer.

We are able to additionally inform the softmax right here shouldn’t be completely fused by counting the variety of read-writes we must always want. In idea it may well simply be one learn and one write (the usual is uh, four so I am bullying a bit). For qk, it might be two reads and one write (the 2 reads can in all probability be saved). The three to 1 ratio then, signifies that the softmax is doing extra reminiscence passes than is perfect. I say this, as a result of this expresses how a lot this counting is software program dependents and wishes experiments to estimate, since in idea the price might be zero.

It is also value noting that the share of time these operations take will get smaller rapidly as mannequin measurement will increase because the reminiscence will enhance on the order of (d_text{mannequin}) whereas the flops enhance on the order of ({d_text{mannequin}}^2) — per layer. The paper is a 336M param mannequin, (d_text{mannequin} = 1024, n_text{layers} = 24).

I added up the latency of all of the values within the “Ours” column that have been reminiscence certain, together with the element-wise operations. The result’s that these intermediate steps take 43% of the time. In a mannequin of measurement 52B (the place (d_text{mannequin}) is 8 occasions bigger, we see these operations grow to be much less vital.

The length of those reminiscence certain intermediate operations will take 8 occasions longer because the operations are vectors of size (d_text{mannequin}). Nonetheless, the variety of flops will enhance by 64 occasions, which suggests the flop time will increase by 64 occasions.

So utilizing the optimisations in that paper, a 52B mannequin inference latency can be about 5% of those intermediate calculations we did not issue into latency.

evaluating in opposition to actual benchmarks

I work at a language modelling firm that has its personal infrastructure and present benchmarks however uh, IP is tough. There’s a sadly small variety of public benchmarks out there for mannequin parallel inferencing? It looks like the one public engines for this are Nvidia FasterTransformer and Microsoft Deepspeed with different benchmarks in all probability scattered in papers I do not know exist. Anywho, we are able to confirm our calculations in opposition to some actual benchmarks!

As a result of I solely need to use 2 GPUs, I’ve run a 13B parameter mannequin with FasterTransformer, which does a bunch of excellent kernel fusing and offers us with tensor parallelism. 13B is 40 layers, 40 heads, every of dim 128 for a dim measurement of 5120. I’ve screenshots of the profiles in here and there are a bunch of attention-grabbing issues in there that may make one other submit.

We’ll begin with a 512 context size, batch measurement 1 and 10 tokens outputted. For a small batch for one token on 2 GPUs we count on 8.4ms, and about 1ms of comms. For 1 GPU, that will be 16.8ms and 0 comms. (2x40x12x5120^2/1.5e12)

Excuse my mangled vital figures, I in all probability ought to’ve stored the mem bandwidth to 1.555 as an alternative of 1.5.

Our empirical end result for 1 GPU is 22.0ms, which means our guess was 76% there. We are able to truly safely account for all of this, the place we all know some share will go to intermediate activations, and that we do not truly get 100% of our theoretical reminiscence bandwidth. For these dimensions, a profile tells us we stand up to about 90% of our full reminiscence bandwidth (the place I evaluate the anticipated price of a matmul to the length of a single matmul kernel and rounded up because the bandwidth utilization varies fairly a bit relying on the tensors being loaded). Counting that in, we count on to take 18.5ms. Including up the price of intermediate activations (which we are able to do from a profile) we get one other 2.2ms, getting us to twenty.7 ms! To account for the final 1.4 ms there are another sub-millisecond operations like token embeddings, doing top-(ok|p), much less web bandwidth than 90% (I could not be bothered to really common all the things I took the best bw utilization I may discover) and even kernal launch occasions.

Our emprical end result for two GPUs is 13.5. We’re farther off this time, for under 62% of the way in which there. We might verify the profile once more to see the reminiscence bandwidth (which we count on to be barely worse, as smaller tensors have a tendency to have the ability to get much less of the bandwidth). This time, it would not fairly get to 90, extra like 87, getting us to 9.5ms. The intermediate activations take an identical period of time (2ms), getting us 11.7ms. With the remaining 1.5 ms then, we’re trying to find comms! That is simply coated by our calculated 1ms of comms not being parallelised. From the profile, our comms take 40-50microseconds per layer, for a complete of 1.7ish ms of comms time, which accounts for all the things fairly properly!

I feel for each of these operations, the counting of intermediate activations was a bit greater than it needs to be, as a result of the profile gave constantly slightly-higher latencies than the uncooked benchmarking run. The output of the benchmark run was 180.86 ms (context time: 45.45 ms) and 283.60 ms (context time: 63.17 ms).

However what in regards to the forwards go? I count on the forwards go to take num_tokens/flops_to_bw_ratio occasions so long as a decoding step. It’s because we’ve got to ship all the tokens to all of the GPUs, and every GPU will do their heads of consideration on it and retailer kv. Let’s use the up to date reminiscence bandwidth, 312e12/(1.5e12x0.9)=231. Trying on the 1 GPU setup, the place 22 is our anticipated decoding step, we see the 22*(512/231) = 48 which isn’t fairly the claimed 63. For two GPUs we get 13.5*(512/231) = 30ms, even worse!

For the one gpu, a number of the lacking time ought to simply be kv storing. Trying on the profiles, that is 18 microseconds per layer, 0.7ms. There are some Memsets for 0.2ms. We count on the flop time (that is flops certain!) for certainly one of our MLP multiplies to be 512x4x5120^2×2/312e12 = 344 microseconds. In apply, that is 476 on the lowest which suggests we get 72% of the flops we count on? For the projection within the consideration we count on we 512×5120^2×2/312e12 = 86 microseconds. In profiles we discover this to be 159 on the lowest, which is 54%. Yikes! I panicked for a bit, however uh that is apparently simply the flops we count on? See Determine 14 in this paper the place a 512x4000x4000 finally ends up getting lower than 150TFLOPs/s.

workout routines

  1. Given batch measurement, context size and next_n, how can we calculate the financial savings of utilizing kv cache?

  2. What overheads does the kv cache add in reminiscence time?

  3. Can we be reminiscence certain on our forwards go however flops certain at every sampling step?

  4. What tradeoffs and calculations ought to we take into account for utilizing extra GPUs than is critical for capability? Say for instance, a 52B mannequin on 8 or 16 GPUs as an alternative of 4.

  5. We got here up with formulation to calculate time to foretell one token. How would we calculate the time to do a complete pattern, from doing the forwards go on the context to predicting all of the tokens requested?

  6. Within the capacity part, I say the reminiscence of intermediate calculations are negligble. How small are they precisely?

  7. Within the batch sizes part, we went a bit off subject and talked in regards to the flops per byte of communication. What are the tradeoffs if we had an embedding dimension measurement of 512?

  8. We assume GPUs hooked up to the identical host right here, however may talk GPUs between hosts like we do in coaching. AWS has 400gb/s. What about it!

  9. In model parallelism, we may in apply talk all of the shards after which have every accelerator do all of the addition, as an alternative of only a share of their addition. What are the latency implications there?

  10. Attempt calculating the big batch velocity for a 52B on 4xGPUs at batch measurement 256. The compute needs to be about 21ms and comms needs to be about 4ms.

  11. Take into account the operation of taking the vector out of the final layer and multiplying it by the unembedding matrix, storing the logits after which doing top-k or top-p sampling (which requires a form). How lengthy ought to this take for a 52B mannequin, and what can we parallelise right here?

  12. How can we shard the token embeddings? Would shard the enter token embeddings in another way from the unembeddings? Layernorms? What further communication does this incur?


Want to lengthen credit score and due to individuals who make a constructive impression on this submit in various capacities. James Bradbury, Eric Zhang, Taylor Rogalski, Horace He, Julian Schrittwieser, Reiner Pope, Jim Wu, Mohammad Bavarian, Tudor Brindus and Adrien Morisot with James main by a protracted shot.


Please cite as:

Chen, Carol. "Transformer Inference Arithmetic",, 2022.

hey kipply you need to higher perceive our large mannequin inferencing latency

sure that is an amazing concept i am going to look into it!

cool i would like to see the profile

if i sit in a darkish room on my own lengthy sufficient i believe i can clarify all of the milliseconds


The architectures and latencies expressed on this submit are these of publicly recognized or theoretical fashions and benchmarks and don’t essentially mirror the architectures or latencies of my employer’s fashions.

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