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True 3D Is A lot Harder Than 2.5D

True 3D Is A lot Harder Than 2.5D

2023-03-23 06:40:11

Creating actual 3D designs is proving to be way more complicated and troublesome than 2.5D, requiring important innovation in each expertise and instruments.

Whereas there was a lot dialogue about 3D designs, there are a number of interpretations about what 3D entails. That is extra than simply semantics, nonetheless, as a result of every packaging choice requires totally different design approaches and applied sciences. And as chips push into the realm of actual 3D-ICs, stacking logic or reminiscence on prime of logic, they grow to be way more difficult to design, manufacture, and finally yield and check.

“To start with, the foundries beginning to supply multi-die packaging, and so they began utilizing this time period 3D-IC,” says John Park, product administration group director within the Customized IC & PCB Group at Cadence. “However It referred to extra than simply silicon stacking and interposers. It additionally included high-density RDL fanouts. It was a time period used to group numerous multi-die, largely foundry-based packaging expertise.”

There have been a number of makes an attempt to type out this terminology. “We’re aligning with imec, which cut up 3D into 4 segments,” says Thomas Uhrmann, director of enterprise improvement at EV Group. “True 3D is wafers stacked on prime of one another in a extremely built-in method. The second group could be 3D system-on-chip (SoC) integration, the place you might need a bottom energy distribution layer, or a wafer-to-wafer stack of reminiscence. The third group consists of 2.5D and silicon interposers. And the ultimate one is 3D system-in-package (SiP), the place contact pitches are about 700 microns, together with fan-out wafer-level packaging. The differentiation is fascinating, as a result of they’re defining the differentiation over contact pitch or integration density.”

This offers a bodily differentiation, however variations additionally will be checked out in different phrases. “The fascinating sorts of 3D are both logic-on-logic, or important memory-on-logic,” says Rob Aitken, a Synopsys fellow. “Each of these are beginning factors, however then you can begin stacking different random issues. I might say that HBM are 3D stacks, however they’re a really particular 3D stack.”

The flows for every of those packaging approaches is totally different. “2.5D and 3D have been used for a number of years to have the ability to assist issues like sensor functions,” says Tony Mastroianni, superior packaging options director at Siemens EDA. “However they don’t use an automatic place-and-route movement, and that’s why I like to make use of the time period ‘true 3D.’ Stacked die expertise as we speak depends on folks doing planning manually. You might be designing every chip so that they butt collectively, however the instruments usually are not doing that. The partitioning and the detailed pin planning are handbook processes.”

True 3D requires a rethinking of the whole movement. “For the environment friendly implementation of an SoC as a 2.5D system, akin to avoiding yield issues or to comprehend greater techniques with extra transistors, current architectures can be utilized,” says Andy Heinig, head of division for environment friendly electronics at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “Solely a chip-to-chip interface should be carried out. However some great benefits of an actual 3D integration can solely be exploited if new ideas and architectures are used.”

Why go to 3D
One of many largest advantages for 3D is decreased distances. “You may make an argument that there’s a square-root-of-two impact,” says Synopsys’ Aitken. “For the entire distances on this stacked object, they grow to be 0.7 of what they might have been within the 2D variant. Because of this, the ability they eat on the wiring half is now 0.7-ish of what it was earlier than as a result of the capacitance is decreased.”

The impression might be bigger than that. “Loads of warmth is generated within the transport of alerts,” says EV Group’s Uhrmann. “For CMOS, you cost and discharge one thing with a view to retailer after which to move on the data. Shrinking and stacking the dies will allow you to make it smaller, so info will be handed within the third dimension. However you in all probability solely have a buffer between them in 3D, moderately than a big PHY and communication protocol.”

Two benefits come from dimension — yield and footprint. “Assuming an identical quantity of logic distributed throughout a number of dies, the yield of your smaller objects shall be greater than the yield of 1 greater object,” says Aitken. “Subsequently, you’ll be able to scale back some degree of price. In fact, you might be growing different prices, however these will come down over time.”

From a 2D footprint perspective, stacking die can considerably scale back space. “By stacking, I can get 3 times the quantity of logic in the identical space,” says Siemens’ Mastroianni. “You find yourself with a a lot smaller footprint with much more logic. So you’ll be able to match much more horsepower in that space, and if in case you have space restrictions it would decrease system prices.”

Heterogeneity might be one other profit. “Heterogeneous expertise architectures are ripe for 3D integration,” says Maurice Steinman, vice chairman of engineering for Lightelligence. “Contemplate combined expertise assemblies, akin to a photonic IC with its companion digital IC. For a few of these integrations, there may be merely no different method to offer the various 1000’s of required die-to-die interconnections with out substantial energy or efficiency sacrifices.”

Mixing applied sciences remains to be primarily uncharted territory. “In case your design doesn’t slot in a reticle dimension, then to have the ability to construct extra gates, it’s essential to go to the true 3D, and that in all probability will keep in the identical expertise,” says Mastroianni. “However there’s actually situations the place you may wish to combine and match. Perhaps you’ve got a compute engine that actually you need within the bleeding edge expertise, however the remainder of the stuff has numerous management that you may do in a much less aggressive course of node.”

That turns into an integration problem. “We now have just lately seen that pure reminiscence on logic configuration works for sure kinds of prospects who’re attempting to resolve the on-chip reminiscence wall drawback,” says Vinay Patwardhan, product administration group director within the Digital & Signoff Group at Cadence. “However numerous prospects wish to have logic on each tiers. For instance, even if you happen to simply have reminiscence on the highest die, then the reminiscence BiST logic or the check logic that goes with the reminiscence must be on that die, as nicely. There’s a want for some logic on that prime die.”

Bodily hierarchy
The mixing of chips right into a 3D stack, and the packaging of that stack, contain a variety of applied sciences, as proven in determine 1.

Fig. 1: 3D packaging versus silicon stacking. Source: Cadence

Fig. 1: 3D packaging versus silicon stacking. Supply: Cadence

Bodily dimensions matter. “For the final word 3D integration, you’re speaking about 14nm pitch, mainly the place transistors are as we speak,” says Uhrmann. “For those who’re speaking about chiplets, that are purposeful IP blocks, you’re within the vary of someplace like micron pitch. There may be near an order of magnitude between transistors stacking and chiplet integration. If you’re forming a 3D bundle, utilizing a 3D chiplet, utilizing a extremely built-in die with a micron pitch, you can not join the micron pitch to the skin world. You continue to have to have the packaging applied sciences with a view to get the routing coarser and coarser, so you finally get them to 400-plus microns on the board degree.”

The pitch defines the combination course of. “There are some huge variations in packaging once we’re packaging a number of dies or a number of chiplets,” says Cadence’s Park. “Chiplets sometimes use what are known as solder-based connections. They’re linked with micro bumps and C4s, and we work with connections which might be normally round 45 microns and bigger to attach these. This additionally creates a packaging hierarchy, as a result of oftentimes we work with black field, summary representations of every of the die or chiplets, and it’s a bundle designer that’s liable for connecting all of them up accurately.”

That normally requires totally different tooling for every. “This can be a multi-scale drawback, which additionally means a multi-physics difficulty,” says Marc Swinnen, director of product advertising at Ansys. “If you go from nanometers on a chip by millimeters on a bundle by centimeters on a 3D-IC interposer, that’s six orders of magnitude you’re crossing there. Historically, these have been dealt with by three totally different units of instruments. Now for 3D-IC, these all should be consolidated right into a single one.”

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Group-splitting causes issues, too. “Most corporations have design teams for ASIC design, and separate inside bundle design teams,” provides Park. “Silicon stacking and 3D has blurred the road between what a bundle engineer is liable for versus the die design staff. We see, greater than ever, the 2 groups in a single room planning the challenge from the early phases. There are numerous necessities for co-design between the domains of bundle and die.”

In some corporations, the interposer additionally was seen as being a PCB inside the bundle, and dealt with by yet one more staff. “3D chips are going to be performing some very superior kind operate, however you’re not essentially going to have the ability to construct your entire system and bundle by stacking dies,” says Mastroianni. “You’ll mix that with different dies on an interposer. Perhaps there shall be a typical processor on the market, or possibly a number of 3D-ICs that you just’re integrating collectively on an interposer. I don’t assume 3D goes to displace to 2.5D. They are going to be complementary. Some functions shall be true 3D, however there shall be an ecosystem ultimately of some chiplets that you just’re going to have the ability to combine and match, and try this in a 2.5D bundle.”

Wherever hierarchy exists, it’s potential for issues to be separated, as long as instruments exist to cowl the boundaries. “We now have to symbolize issues in a hierarchy type since you’re not designing a single monolithic chip anymore,” says Park. “You’re designing a system, and so there are new issues that come into play like system LVS (format versus schematic). Are the hybrid bonds all aligned? Are the connections going as you count on them, from the highest die by the underside die? There’s a hierarchy simply in the truth that you’ve got a hierarchy representing die and you’ve got a hierarchy representing the system-level design. Design, by nature, is hierarchical as a result of it’s a system-level design that has embedded in it die-level designs.”

Logical hierarchy
Hierarchy is a should in any complicated design, however 3D provides an fascinating twist to it. “If you’re doing conventional place-and-route for big designs, you’re utilizing a hierarchical design strategy,” says Mastroianni. “You break the design up into blocks, and people blocks undergo place-and-route, and then you definitely do your top-level integration. For 3D, we are able to primarily use the identical course of, however we’re including one other degree of hierarchy. Contemplate a 9 billion-gate design, the place we break this into three chips, every with 3 billion gates. Basically, you simply have to specify which blocks will go on chip 1, which blocks will go on chip 2, and people who would be the blocks in chip 3. No less than within the close to time period, instruments won’t be able to routinely determine which logic to place the place, and do a real 3D world place-and-route at that degree. There are some longer-term DARPA proposals that need to try this, however even these proposals usually are not within the first section.”

Some new instruments could be required to confirm the chip-to-chip connectivity. “We’d sometimes be utilizing a typical flop-to-flop connection,” says Park. “So we want STA instruments, timing-driven routing, timing-driven placement, and as an alternative of a buffer separating the units, it’s only a hybrid bond. It’s only a small parasitic worth that comes into play. For this, we are able to’t work on the summary degree, like conventional packaging, the place these are handled as black packing containers. We now have to symbolize every of the chips or chiplets on the full element degree — full transistor degree if its analog design, normal cell macro degree if it’s a digital design — as a result of we’ve to have the ability to mannequin the whole lot. As an alternative of modeling the whole lot from a 2D perspective, it needs to be carried out with this new vertical path integration.”

That will require compromises. “You may both have a real 3D signoff of the logic stacked object, or you’ll be able to simply say, I’m solely going to run paths which might be two inverters lengthy between the die,” says Aitken. “Then no matter corners they’re, they may simply line up and I don’t have to fret about it.”

There may be widespread settlement that doing it flat is just not an choice. “It could be a major problem for any of the EDA instruments, simply due to the quantity of knowledge,” says Cadence’s Patwardhan. “Some efficient abstraction strategies are wanted, and hierarchy definition is the very first thing that’s fashionable and is working. We now have discovered, utilizing design hierarchy, in addition to partitioning a design, the right way to make evaluation run on a partitioned design. What assumptions will be made and nonetheless have accuracy pretty much as good as signoff. It should occur, because it occurred within the 2D SoC. Smaller designs will first set up a full flat run and the extent of accuracy wanted, (measured versus modeled). As we go ahead, as bigger chips get carried out in a silicon stack format, there shall be some correlation that EDA, OSATs, and foundries must show between a hierarchical methodology and the flat methodology, to be inside a sure margin. And if that’s obtainable, then you’ll be able to comfortably say that your full flat run goes to look the identical. It’s a vital methodology in 3D-IC design, and it received’t be all flat.”

This turns into much more troublesome when full 3D place-and-route turns into potential. “The protected reply as we speak is to say, ‘Let’s not divide blocks. Let’s simply hold every block on one die and we’ll speak to them throughout the die boundary.’ Doing that, you continue to have a 3D placement partitioning drawback that you need to resolve, however your signoff drawback is easier as a result of not less than your block signoff is confined to the 2D house,” says Aitken. “Educational works recommend that transferring blocks and interspersing them throughout a boundary can achieve you additional profit. However for probably the most half, these papers have ignored issues like clock synchronization, die matching, and different issues that can present up while you attempt to do one thing like that. For those who hold particular person blocks on a single die, you continue to have an entire lot of issues to resolve, however it’s a smaller variety of issues than if you happen to permit the blocks emigrate throughout the die.”

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