Verilog to Routing
The Verilog to Routing (VTR) challenge offers open-source CAD instruments for FPGA structure and CAD analysis. This challenge, together with the benchmark suites, is launched underneath the MIT license. Which means that you’re free to make use of, modify, and distribute the software program and benchmark information, topic to the phrases and situations of the MIT license.
Open supply CAD instruments allow the investigation of latest FPGA architectures and CAD algorithms, which aren’t potential with closed-source instruments.
The VTR design stream takes as enter a Verilog description of a digital circuit, and an outline of the goal FPGA structure. It then perfoms:
- Elaboration & Synthesis (ODIN II)
- Logic Optimization & Expertise Mapping (ABC)
- Packing, Placement, Routing & Timing Evaluation (VPR)
to provide FPGA velocity and space outcomes.
VTR may produce the data required for bitstream technology to focus on actual FPGA units.
VTR is versatile and might taget a variety of hypothetical, commercial-like and business FPGA architectures, and contains benchmark designs appropriate for evaluating FPGA architectures.
For extra data see the documentation.
