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What Does Including 50 Do? – Chips and Cheese

What Does Including 50 Do? – Chips and Cheese

2023-04-01 03:03:33

Observe the publish day of this text. There will probably be a correct one on Terascale 3 afterward, don’t fear. However for now, completely satisfied April Fools Day!

Status is every part for pc {hardware} producers. A number of proportion factors could not make or break somebody’s gaming expertise, or make some new workload accessible to the plenty; however it does enhance a producer’s repute. A tangential query, then, is what would occur if we elevated the mannequin quantity by just a few proportion factors. 6950 is 0.7% increased than 6900, in any case. So, what does such a rise to the mannequin quantity get you?

They give the impression of being nearly the identical. Proper?

Thankfully, we are able to determine this out in all of the element we’re used to. I’ve an AMD Radeon HD 6950 to check to the Radeon RX 6900 XT. Ideally I might examine the 6950 XT and 6900 XT, however that might price cash.

Evaluating Architectural Constructing Blocks

The Radeon HD 6950 and Radeon RX 6900XT use very totally different architectures, though each merchandise belong to the 6000 collection and share a model title. AMD’s Radeon HD 6950 makes use of the Terascale 3 structure. Terascale 3’s constructing blocks are referred to as SIMD Engines, and the HD 6950 has 22 of them enabled out of 24 on the die. Like GCN, Terascale 3 runs in wave64 mode. Meaning every instruction works throughout a 64-wide vector. Every ingredient is 32 bits large, making it a bit like AVX-2048.

As a result of the SIMD Engine has a 16-lane execution unit, the 64-wide wave is executed over 4 cycles. A single thread can’t execute directions again to again due to register port conflicts, so directions successfully have eight cycle minimal latency, and a SIMD engine wants at the least two waves in flight to maintain the execution unit busy. Every execution lane is VLIW4, which means it’s 4 parts large; so the SIMD can execute 64 FP32 operations per cycle. With VLIW packing in thoughts, a SIMD would wish 64 * 2 * 4 = 512 operations in flight in an effort to attain its most compute throughput.

MSPaint-ing an AMD slide to indicate how a lot work in flight that you must absolutely make the most of FP32 lanes. Additionally I don’t know why I left GCN in right here.

In distinction, RDNA 2 focuses on making the execution items straightforward to feed. It makes use of a lot bigger constructing blocks as nicely, referred to as Workgroup Processors, or WGPs. Every WGP consists of 4 32-wide SIMDs, which might execute both wave32 or wave64 directions. These SIMDs are akin to Terascale’s SIMD engines, in that each have their scheduler feeding an execution unit. Nonetheless, RDNA 2 SIMDs are far simpler to feed. They will full a 32-wide wave each cycle, and execute directions from the identical thread again to again. They don’t want VLIW packing both. In actual fact, a WGP with 128 FP32 lanes solely wants 128 operations in flight to completely make the most of these execution items.

Instruction Throughput

Terascale 3 and RDNA 2 have totally different priorities in the case of execution unit design. For a fairer comparability, the 6900 XT is compelled into CU mode for instruction charge testing. Meaning the LDS is partitioned into two 64 KB sections. If we run a single workgroup, it has to remain on one half of a WGP, with 64 lanes. Comparisons are simpler if we are able to examine 64 lanes to 64 lanes, proper? I’ve additionally locked the 6900 XT to the identical 800 MHz clock pace so I can divide by 0.8 for per-cycle throughput throughout each GPUs, saving just a few keypresses in Excel.

Huh, the graph kinds look a bit totally different. I suppose it’s an Excel 2007 day.

The HD 6950 has spectacular FP64 efficiency, although it does take a little bit of coaxing to get most efficiency out of the design. AMD’s outdated driver is susceptible to translating a * b + c into separate FP64 multiplies and provides. It received’t emit a FMA_64 instruction until you employ the OpenCL MAD() perform, which prefers pace over accuracy. Due to this fact, you must be MAD to get probably the most out of Terascale 3’s FP64 efficiency. However even should you dislike being MAD, Terascale 3 remains to be a really competent FP64 performer in comparison with RDNA 2.

Below the hood, Terascale 3’s register file is organized into 4 banks, named X, Y, Z, and W. FP64 is handled through the use of the corresponding registers in a pair of banks to retailer a 64-bit worth, and utilizing a pair of VLIW lanes (XY or ZW) to carry out the calculation. Every VLIW lane can solely write a end result to its corresponding register financial institution, and the identical restriction applies for FP64.

For comparability, the 6900 XT is a horrible FP64 performer. The HD 6950 got here out at a time when folks have been questioning if GPU compute could be broadly used, with some fantasizing about GPUs performing like a second FPU. Good FP64 throughput could be helpful for offloading a greater diversity of workloads, as a result of FP64 is used loads with CPUs. In distinction, RDNA 2 got here out when GPU compute was clearly a secondary position for shoppers.

RDNA 2 has a bonus with particular features like reciprocal and inverse sq. root, although humorous sufficient the throughput for these features didn’t change between CU mode and WGP mode. Perhaps there’s one 32-wide unit shared throughout the whole WGP, who is aware of.

Tough sketch of execution unit layouts for 64 lanes.

The identical doesn’t apply to 32-bit integer multiplication, which can be handled as a particular perform of kinds for each architectures. It has loads much less throughput. Like different particular features on Terascale 3, integer multiplication is executed by issuing one instruction throughout a number of of the VLIW lanes. Older Terascale variants had a separate T lane for dealing with particular features, however that lane was typically arduous to feed resulting from register bandwidth constraints and instruction stage parallelism limitations.

Each architectures can execute the extra widespread 32-bit integer provides at full charge. RDNA 2 has a big benefit for 16-bit integer operations, as a result of it may pack two of them into one 32-bit register, and may configure the integer ALU to execute that at double charge. In distinction, Terascale 3 has no 16-bit integer ALUs. It merely reuses the 32-bit ALUs for decrease precision operations, after which masks the outcomes (or makes use of bitfield insert) to get a 16-bit worth.

For 64-bit integer operations, each architectures use add-with-carry directions as a result of they don’t have 64-bit vector integer ALUs. In concept, each ought to execute them at half charge. However do not forget that little element about how every Terascale lane can solely write to its corresponding register financial institution? AMD’s compiler finally ends up losing ALU slots to maneuver register values round, decreasing throughput.


Having execution items is enjoyable, however feeding them will not be. Once more RDNA 2 emphasizes feeding the execution items. It has a posh cache hierarchy with extra cache ranges than your typical CPU. Every pair of SIMDs has a 16 KB L0 cache, which acts as a primary stage cache for all types of reminiscence accesses. Every shader engine has a 128 KB L1 cache, which primarily serves to catch L0 misses and simplify routing to L2. Then, a 4 MB L2 serves as the primary, GPU-wide read-write cache with multi-megabyte capability. Lastly, a 128 MB Infinity Cache helps cut back reminiscence bandwidth calls for. RDNA 2’s caches are extremely optimized for each graphics and compute. Non-texture accesses can bypass the feel items, enabling decrease latency.

To additional enhance compute efficiency, RDNA 2 has separate vector and scalar caches. On the vector facet, the WGP’s 4 SIMDs are break up into two pairs, every with its personal vector cache. That association permits increased bandwidth, in comparison with a hypothetical setup the place all 4 SIMDs are hammering a single cache. 128B cache traces additional assist vector cache bandwidth, as a result of solely a single tag test is required to get a full 32-wide wave of information. On the scalar facet, there’s a single 16 KB cache optimized for low latency. It makes use of 64B cache traces and is shared throughout the whole WGP, serving to to make extra environment friendly use of cache capability for stuff like shared constants.

Terascale 3 is the alternative. It has a easy two-level cache hierarchy, with small caches throughout. Every SIMD engine has a 8 KB L1 cache, and the entire GPU shares a 256 KB L2. There’s no separate scalar reminiscence path for values that keep fixed throughout an a wave. In contrast to RDNA’s common goal caches, Terascale’s caches hint their lineage to texture caches in pre-unified-shader days. They’re not optimized for low latency. Reminiscence hundreds for compute kernels mainly execute as vertex fetches, whereas RDNA 2 can use specialised s_load_dword or global_load_dword directions that bypass the TMUs.

We will’t fully blame the caches both. Terascale 3 organizes several types of directions into clauses. It has to change to a texture clause to fetch knowledge from caches or VRAM, then to an ALU clause to truly use the information. A clause change carries vital latency penalties. Terascale directions themselves endure from excessive latency as a result of they execute over 4 cycles, after which have to attend 4 extra cycles earlier than the thread can execute once more. Meaning handle era takes longer on Terascale. RDNA 2 is much better on this regard as a result of it doesn’t have a clause change latency and may execute directions with decrease latency. To make issues worse for Terascale 3, RDNA 2 clocks greater than twice as excessive though it has a decrease mannequin quantity.

Discover the clauses in Terascale meeting. And no clauses on RDNA 2

However the next mannequin quantity does assist in one case. Comparatively talking, Terascale 3 is best if we use texture accesses. That’s as a result of we’re utilizing the TMUs to assist with handle era, as a substitute of working in opposition to them. Nonetheless, the HD 6950’s latency is brutal in an absolute sense.

RDNA 2 takes a surprisingly mild penalty from hitting the TMUs.The buffer_load_dword directions take longer than the scalar s_load_dword ones, however they really do higher than vector accesses (global_load_dword).

Native Reminiscence (LDS)

When GPU packages want constant, low latency accesses, they will convey knowledge into native reminiscence. Native reminiscence is simply shared between small teams of threads, and acts as a small, excessive pace scratchpad. On AMD GPUs, native reminiscence maps to a construction referred to as the Native Knowledge Share (LDS). Every Terascale 3 SIMD Engine has a 32 KB LDS, whereas every RDNA 2 WGP has a 128 KB LDS.

Sadly, the next mannequin quantity doesn’t assist and Terascale’s LDS has greater than 4 occasions as a lot latency as RDNA 2’s. Nonetheless, the HD 6950 does find yourself someplace close to Intel’s HD 530. So perhaps, the next mannequin quantity has advantages, as a result of it brings you nearer to the place an even bigger firm was.

Yay, no extra clause switching on Terascale. LDS ops can merely use the X lane from inside an ALU clause

Additionally, what about LDS bandwidth? Terascale 3’s LDS can ship 128 bytes per cycle to its SIMD Engine. RDNA 2’s LDS can ship 128 bytes per cycle to every pair of SIMDs. Sadly testing bandwidth is tough due to handle era overhead and needing to do one thing with the outcomes so the compiler doesn’t optimize it out. However right here’s an early try:

Nope. We’re actually beginning to see that including 50 to the mannequin quantity doesn’t assist. 6950 is over 13 occasions increased than 530 although, so perhaps there’s nonetheless a bonus. Extra particularly the HD 530’s three subslices every have a 64 byte per cycle knowledge port to each the LDS and L3. Distinction that with Terascale, which has a 128 byte per cycle path to the LDS inside every SIMD. I suppose in case your mannequin quantity is just too low, you make nonsensical architectural selections.

Cache Bandwidth

From a single constructing block’s perspective, RDNA 2 has a large benefit. The HD 6950 could have the next mannequin quantity, however the 6900 XT advantages from increased – a lot increased – clock speeds, a extra fashionable cache hierarchy, and larger constructing blocks. A WGP merely has extra lanes than a SIMD Engine. It’s good to see the cache hierarchy once more from a bandwidth perspective. However simply as with latency, the HD 6950 will get destroyed.

The next mannequin quantity could also be nice for advertising and marketing, however clearly it means smaller constructing blocks and a weaker cache hierarchy. However even when we set the 6900 XT to CU mode, 64 lanes fare much better with the identical stage of parallelism.

Let’s have a look at shared elements of the reminiscence hierarchy too, and the way they deal with bandwidth calls for as extra SIMD Engines or WGPs get loaded up. Most elements of graphics workloads are extremely parallel, so shared caches have the unenviable job of servicing a whole lot of excessive bandwidth shoppers.

Once more, Terascale 3 will get completely crushed. The L2 exams are probably the most comparable ones right here, as a result of it’s the primary cache stage shared throughout the whole GPU. The 6900 XT can ship round ten occasions as a lot L2 bandwidth regardless of having a decrease mannequin quantity. RDNA 2’s efficiency benefit right here is definitely understated as a result of it has a write-back L2 cache. Terascale 3’s L2 is a texture cache, which means that it may’t deal with writes from the shader array. Writes do undergo some write coalescing caches on the way in which to VRAM, however as their title suggests, these caches aren’t massive sufficient to insulate VRAM from write bandwidth calls for.

RDNA 2 has an extra stage of cache past L2. With 128 MB of capability, the Infinity Cache primarily serves to scale back VRAM bandwidth calls for. In different phrases, it trades die space to allow a less expensive VRAM setup. Although Infinity Cache doesn’t serve the identical position because the L2, it’s additionally a shared cache tied to a reminiscence controller partition. It additionally stomps the HD 6950’s L2 by a large margin. CU mode takes somewhat longer to ramp up, however finally will get to the identical staggering bandwidth.

See Also

Out in VRAM, the HD 6950 does comparatively higher. It nonetheless loses, however solely by a 3x margin. The upper mode quantity does rely for one thing right here as a result of Terascale 3 can ship extra bytes per FLOP, doubtlessly which means it’s much less bandwidth certain for bigger working units. That’s, should you don’t run out of VRAM within the first place.

Nonetheless, the 6900 XT has a large bandwidth benefit in absolute phrases. GDDR6 can present way more bandwidth than GDDR5.

What About Greater Numbers

Up to now, we’ve seen that including 50 to the mannequin quantity has not produced any actual benefits. The HD 6950 could also be comparatively environment friendly by way of utilizing little or no management logic to allow a whole lot of compute throughput. It might need extra VRAM bandwidth relative to its FP32 throughput. However the 6900 XT is best in an absolute sense, throughout all of these areas. A few of this may be attributed to the method node too. On that word, TSMC’s 40 nm course of has an even bigger quantity than their 7 nm course of. However once more, larger numbers don’t assist.

But, AMD’s most up-to-date card has elevated mannequin numbers even additional. The RX 7900 XTX’s mannequin quantity is 1000 increased than the RX 6900 XT’s. Such a large enhance within the mannequin quantity has created extra downsides. Although the HD 6950 has the next mannequin quantity, it wasn’t excessive sufficient to trigger points with clock speeds.

However incrementing the mannequin quantity by such a large quantity impacted clocks too. Usually we don’t have a look at first stage cache bandwidth scaling, as a result of it’s boring. Every SM or CU or WGP or SIMD Engine has its personal first stage cache, so that you get a straight line and straight will not be cool.

However that adjustments with RDNA 3. If the entire WGPs are loaded, clocks drop by greater than 15%. Clock drops aren’t a very good factor. If RDNA 3 may maintain 3 GHz clocks throughout all workloads, it will compete with the RTX 4090. In the identical manner, the Ryzen 9 7950X would dominate every part if it may maintain 5.7 GHz no matter what number of cores are loaded. This clocking habits is certainly due to the upper mannequin quantity.

If AMD went with a decrease mannequin quantity, RDNA 3 would be capable to keep excessive clock speeds below heavy load, simply because the 6950 and 6900 did. Sadly, AMD used 7950 for his or her high finish RDNA 3 card. In the event that they didn’t, a 15% clock enhance would possibly allow them to compete instantly with the RTX 4090.


AMD mustn’t proceed to extend mannequin numbers. Doing so can lower efficiency throughout quite a lot of metrics, as knowledge from the HD 6950 and RX 6900 XT reveals. As a substitute, they need to maintain the mannequin quantity in place and even lower it to make sure future generations carry out optimally.

If AMD retains the mannequin quantity fixed, what may they do to correctly differentiate a brand new card? Nicely, the reply seems to be suffixes.

Including a ‘XTX’ suffix has given RDNA 3 a big cache bandwidth lead over the HD 7950. The identical benefit applies elsewhere. For his or her subsequent era, AMD ought to launch a Radeon RX 7900 Ti XTX SE Professional VIVO Founders Version in an effort to get the suffix benefits, with out the mannequin quantity enhance disadvantages.

No XT means decrease energy necessities I suppose? So solely two 6-pin connectors are wanted

Nonetheless, AMD ought to be cautious about including too many suffixes. Going from the 6950 to the 6900 XT elevated the variety of energy connectors from two to 3. A hypothetical Radeon RX 7900 Ti XTX SE Professional VIVO Founders Version could have eight energy connectors. Customers working funds provides could not be capable to use the cardboard, until they make ample use of six-pin to eight-pin adapters, and eight-pin to dual eight-pin adapters after that. On an unrelated word, all the time ensure you test the hyperlink goal earlier than you click on and purchase.

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