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What’s a MCR DIMM or Multiplexer Mixed Ranks DIMM

What’s a MCR DIMM or Multiplexer Mixed Ranks DIMM

2023-04-01 07:43:23

SK Hynix MCR DIMM Diagram
SK Hynix MCR DIMM Diagram

One of many greatest challenges of contemporary servers is reminiscence bandwidth. To that finish, server designers are taking a look at MCR DIMMs or Multiplexer Mixed Ranks DIMMs for the 2024-2025-era of servers (and past) to get round present reminiscence bandwidth constraints. We needed to get forward of the pattern and focus on the expertise a bit extra for our readers.

What’s a MCR DIMM or Multiplexer Mixed Ranks DIMM?

In the event you noticed our latest Memory Bandwidth Per Core and Per Socket for Intel Xeon and AMD EPYC piece you will have seen the reminiscence bandwidth problem in servers.

Intel And AMD Theoretical Bandwidth Growth For Mainstream Servers 2013 2023
Intel And AMD Theoretical Bandwidth Progress For Mainstream Servers 2013 2023

CPUs proceed to extend core density and it’s a problem for reminiscence bandwidth to maintain up. One innovation within the present era of servers is DDR5 that we coated in Why DDR5 is Absolutely Necessary in Modern Servers.

There are three primary methods server designers are fixing for reminiscence bandwidth challenges:

  • Enhance DDR speeds
  • Enhance DDR channels
  • Enhance sources of reminiscence bandwidth (e.g. including CXL units)
  • Use extra specialised reminiscence like HBM

That pursuit has led us to motherboards like this one from Gigabyte:

Gigabyte G493 ZB0 AMD EPYC Genoa GPU Server At SC22 Memory Slots
Gigabyte G493 ZB0 AMD EPYC Genoa GPU Server At SC22 Reminiscence Slots

Right here we’ve an AMD EPYC Genoa 2P platform with a full set of 48 DIMMs. As one can see, the sockets have to be offset by ~8-9 DIMMs as a result of there’s merely not sufficient room in a normal 19″ server so as to add DIMM slots. One of these configuration provides over 5 inches to a server making it a bit much less sensible. In consequence, many AMD EPYC 9004 “Genoa” servers are 12 DIMM per socket designs as that’s the most reminiscence bandwidth configuration.

Microsoft Azure HBv4 Dual AMD EPYC Genoa And FPGA At SC22 2
Microsoft Azure HBv4 Twin AMD EPYC Genoa And FPGA At SC22 2

As CPU sockets get greater, becoming even these 12 reminiscence channels turns into troublesome, so we at the moment are at a degree the place server designers want a brand new approach to develop reminiscence bandwidth past simply including extra DDR5 slots. Bodily, including extra slots is close to its restrict.

In consequence, the following era of DDR5 reminiscence shall be MCR DIMMs. SK hynix introduced its DDR5 MCR DIMM on the finish of 2022, however the influence goes to be felt in 2024/ 2025 and later.

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MCR DIMMs are in a position to concurrently function two ranks and ship 128bytes to a CPU (64 bytes from every rank) roughly doubling the efficiency per DIMM. The MCR DIMM makes use of an information buffer on the modules to assist mix transfers from every rank.

SK Hynix MCR DIMM Diagram
SK Hynix MCR DIMM Diagram

Whereas the present DDR5 is 4.8Gbps, the MCR DIMM is being focused at 8Gbps as a place to begin, and going up from there. Whereas we are going to get an interim step in DDR5 speeds in 2023 and early 2024, that is going to be an infinite soar for servers in late 2024 and into 2025.

Last Phrases

Whereas NVIDIA’s Grace Superchip Features 144 Cores 960GB of RAM and 128 PCIe Gen5 Lanes together with nearly 1TB/s of reminiscence bandwidth, it’s utilizing LPDDR5X reminiscence and thus is proscribed in capability. MCR DIMMs ought to enable normal server processors to proceed rising reminiscence capability whereas additionally reaching effectively over that 1TB/s of reminiscence bandwidth in dual-socket servers.

Apart from MCR DIMMs, we count on CXL Reminiscence Growth to be extra commonplace by 2025, including further reminiscence bandwidth, albeit at a better latency.

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